When using the R-Tile Avalon Streaming IP for PCI Express* how should the CPL Always Grant option be used?
Description CPL Always Grant is a new option in the GUI for the R-Tile Avalon Streaming IP for PCI Express. If the parameter is turned on, internally generated TLPs (completion and message) will check for available credits at the link partner (i.e., total credit) and will not be limited to the locally allocated credit of 1, 4, or 16, depending on the scale factor used. If the parameter is turned off, which is the default: Consider that there are 100 completion credits available and we allocated 4 credits for internally generated completions. After 4 config reads are received and after the Hard IP has sent 4 completions in response, the 5th config read received will not result in a completion being transmitted by the Hard IP until a credit update is received from the Root Port, even though the Hard IP still has 96 credits available for completions. This behaviour applies only to configuration requests which require completions to be generated by the PCIe Hard IP. Internally generated messages are posted and do not require completions to be generated. The FC_Update check is not bypassed when the CPL Always Grant option is turned on. The Hard IP keeps track of available credits at the link partner and prevents any TLPs (internal or user- generated) from being transmitted through the link enough credits are not available. For header and data, the credits reserved for internal IP usage are 1, 4, and 16 for scaling factors of 1, 4, and 16 respectively. Header credits and data credits have their own allocation. For new designs targeting an interoperable vendor-neutral system architecture, Altera recommends that this option be enabled. Resolution This information is scheduled to be included in a future release of the R-Tile Avalon Streaming IP for PCI Express User Guide.
What is the latest device firmware for the Agilex® FPGA and Stratix®10 FPGAs?
Description Altera® recommends using the latest version of the Quartus® Prime Pro Edition Software and the latest available device firmware. Please also see the following user guides: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution The latest device firmware available for the Quartus® Prime Pro Edition Software can be downloaded from the following links: Quartus Prime Pro Edition Software version 25.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.3? Quartus Prime Pro Edition Software version 25.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1? Quartus Prime Pro Edition Software version 24.3.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3.1? Quartus Prime Pro Edition Software version 24.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3? Quartus Prime Pro Edition Software version 24.2 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.2? Quartus Prime Pro Edition Software version 24.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.1? Quartus Prime Pro Edition Software version 23.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.4? Quartus Prime Pro Edition Software version 23.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.3? Quartus Prime Pro Edition Software version 23.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.2? Quartus Prime Pro Edition Software version 23.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.1? Quartus Prime Pro Edition Software version 22.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.4? Quartus Prime Pro Edition Software version 22.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.3? Quartus Prime Pro Edition Software version 22.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.2? Quartus Prime Pro Edition Software version 22.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.1? Quartus Prime Pro Edition Software version 21.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.4? Quartus Prime Pro Edition Software version 21.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.3? Quartus Prime Pro Edition Software version 21.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.2? Quartus Prime Pro Edition Software version 21.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.1? Quartus Prime Pro Edition Software version 20.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 20.3?Why is there an "unrecognized device" error when using quartus_jli to configure or program a JAM file for flash devices of 2 GB or larger?
Description In any versions of Altera® Quartus® Prime Pro Edition Software, the quartus_jli command may report an “unrecognized device” error when a JAM file targets a flash device that is 2 GB or larger. This behavior is specific to JAM files used with large flash devices and does not occur with smaller flash sizes. Resolution Use the following workaround to avoid the error: Run the jtagconfig command to detect the connected JTAG hardware. After the hardware is detected, run quartus_jli to configure or program the JAM file. There is currently no plan to fix this behavior in a future Quartus® Prime release.Why are my high fanout cells not duplicated?
Description Due to an problem in the Quartus® Prime Pro Edition Software versions 24.3 and later, duplication of cells with high fanout is prevented even when duplication assignments such as DUPLICATE_REGISTER or DUPLICATE_SYNC_FANIN are defined explicitly. This behavior affects cells that have a driver in a different partition, including both signals and clocks. For example, a register in partition A that has its clock coming from the root partition will not be duplicated despite having the appropriate assignment. Resolution To work around this problem, remove the partitions or ensure that the affected cells are not driven by other cells in different partitions. If removing partitions from your design is not feasible, patches are available to work around this problem. Download and unzip the zip file that matches your Quartus® Prime Pro version and operating system from this KDB. Quartus® Prime Pro Edition Version Patch number 24.3 [0.36|^quartus-24.3-0.36.zip] 24.3.1 [1.30|^quartus-24.3.1-1.30.zip] 25.1 [0.38|^quartus-25.1-0.38.zip] 25.1.1 [1.29|^quartus-25.1.1-1.29.zip] 25.3 [0.28|^quartus-25.3-0.28.zip] 25.3.1 [1.07|^quartus-25.3.1-1.07.zip] Patches for versions 25.3 and 25.3.1 also address additional problems; refer to the README files for more information. This problem is fixed beginning with the Quartus® Prime pro Edition Software version 26.1.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_2
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the error above when using the I/O PLL Parameterizable Macro (ipm_iopll). The error only occurs when using non-integer values for the VCO Clocks and Output Clocks in the I/O PLL Parameterizable Macro. Resolution To work around this problem, use non‑integer values for the VCO Clocks and Output Clocks in the IOPLL IP. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.drivers/src/altera_s10_mailbox_client.c:32:59: error: 'OS_FLAG_SET' undeclared (first use in this function); did you mean 'ALT_FLAG_SET'?
Description Due to a problem Quartus® Prime Pro Edition Software, you might see an error when compiling Nios® V software with the mailbox Client IP and FreeRTOS because the driver software of the IP doesn't support FreeRTOS. Resolution The driver software supports Hardware Abstraction Layer(HAL) and uCOS-II. Please select one of them when generating Nios® V BSP.Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Error when using Riviera Pro or Siemens Questa* with version 25.3?
Description Due to a problem in version 25.3 of the Quartus® Prime Pro Edition Software, simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* will Error when using Riviera Pro or Siemens Questa*. 1. Examples of the errors in Siemens Questa* can be seen below: > # ** error (suppressible): ctfb_hssi_atoms.sv(402484): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_10_addr' not found for override. > # ** error (suppressible): ctfb_hssi_atoms.sv(402485): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_11_addr' not found for override. > # ** error (suppressible): ctfb_hssi_atoms.sv(402486): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_12_addr' not found for override. > # ** error (suppressible): ctfb_hssi_atoms.sv(402487): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_13_addr' not found for override. > # ** error (suppressible): ctfb_hssi_atoms.sv(402488): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_14_addr' not found for override. > # ** error (suppressible): ctfb_hssi_atoms.sv(402489): (………. 2. Examples of the errors in Riviera Pro can be seen below: > # ELAB2: Fatal Error: ELAB2_0036 pcie_auto_tiles.sv (70278): Unresolved hierarchical reference to "z1577b_x393_y0_n0.z1577b_u_pcie_ss__u_ctop__ub_ctrltop__virtual_pcie_x4x4x4_ep" from module "pcie_ed_sim_tb.dut_pcie_tb_ip.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.tile_bfm" (module not found). > # KERNEL: Error: E8005 : Kernel process initialization failed. > # VSIM: Error: Simulation initialization failed. Resolution To workaround this problem in version 25.3 of the Quartus® Prime Pro Edition Software, the errors can be suppressed by adding "-supress 2732" to the USER_DEFINED_COMPILE_OPTIONS, and "-supress 10000" to the USER_DEFINED_ELAB_OPTIONS in your simulation scripts. To workaround in Riviera Pro, remove 2 lines from the simulation script as detailed below: cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/aldec open up file: run_riviera.tcl and remove line: set DEVICES_SIM_LIB_DIR $env(QUARTUS_ROOTDIR)/../devices/sim_lib2 set QUARTUS_SIM_LIB_DIR $env(QUARTUS_ROOTDIR)/eda/sim_lib2 run command: vsim -do run_riviera.tcl This problem has been fixed starting with Quartus® Prime Pro Edition Software version 25.3.1.
What Agilex® 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe® REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Resolution This information has been scheduled for inclusion in the next release of the Agilex® PCI Express* IP User Guides. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_traversal_manager.cpp, Line: 2769
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 to 25.3.1, you might see this internal error at the Fitter Finalize stage when the design contains combinational loops. Static Timing Analysis analyzes timing graphs without loops. When a combinational loop is detected, Timing Analyzer replaces the loop with bypass edges whose delays represent the longest path through the loop. When new timing corners are added later in the finalize stage, the bypass edge delays may not be computed for all corners, causing an internal consistency check to fail and resulting in an internal error. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.