Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Error when using Riviera Pro or Siemens Questa* with version 25.3?

Description

Due to a problem in version 25.3 of the Quartus® Prime Pro Edition Software, simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* will Error when using Riviera Pro or Siemens Questa*.

1. Examples of the errors in Siemens Questa* can be seen below:

> # ** error (suppressible): ctfb_hssi_atoms.sv(402484): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_10_addr' not found for override.
> # ** error (suppressible): ctfb_hssi_atoms.sv(402485): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_11_addr' not found for override.
> # ** error (suppressible): ctfb_hssi_atoms.sv(402486): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_12_addr' not found for override.
> # ** error (suppressible): ctfb_hssi_atoms.sv(402487): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_13_addr' not found for override.
> # ** error (suppressible): ctfb_hssi_atoms.sv(402488): (vopt-2732) module parameter 'u_pcie_ss__u_ctop__ub_core8__pf0_reserved_14_addr' not found for override.
> # ** error (suppressible): ctfb_hssi_atoms.sv(402489): (……….
 

2. Examples of the errors in Riviera Pro can be seen below:

> # ELAB2: Fatal Error: ELAB2_0036 pcie_auto_tiles.sv (70278): Unresolved hierarchical reference to "z1577b_x393_y0_n0.z1577b_u_pcie_ss__u_ctop__ub_ctrltop__virtual_pcie_x4x4x4_ep" from module "pcie_ed_sim_tb.dut_pcie_tb_ip.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.tile_bfm" (module not found).

> # KERNEL: Error: E8005 : Kernel process initialization failed.

> # VSIM: Error: Simulation initialization failed.

Resolution

To workaround this problem in version 25.3 of the Quartus® Prime Pro Edition Software, the errors can be suppressed by adding "-supress 2732" to the USER_DEFINED_COMPILE_OPTIONS, and "-supress 10000" to the USER_DEFINED_ELAB_OPTIONS in your simulation scripts.

To workaround in Riviera Pro, remove 2 lines from the simulation script as detailed below:

1. cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/aldec
2. open up file: run_riviera.tcl and remove line:
   1. set DEVICES_SIM_LIB_DIR $env(QUARTUS_ROOTDIR)/../devices/sim_lib2
   2. set QUARTUS_SIM_LIB_DIR  $env(QUARTUS_ROOTDIR)/eda/sim_lib2
3. run command: vsim -do run_riviera.tcl

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.