What Agilex® 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe® REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Resolution This information has been scheduled for inclusion in the next release of the Agilex® PCI Express* IP User Guides. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why does Quartus® Prime Pro Edition version 25.1.1 and later add a phased_clk_lock_interface conduit to the altera_eth_1588_tod IP when targeting Agilex® 7 FPGA devices?
Description In Quartus® Prime Pro Edition software version 25.1.1 and later, when targeting Agilex® 7 FPGA devices, the altera_eth_1588_tod IP exposes an additional phased_clk_lock_interface conduit. This interface conduit was not present in earlier Quartus® Prime Pro Edition versions. As a result, designs that were originally created and validated using Quartus® Prime Pro Edition version 25.1 or earlier may encounter connectivity issues or appear broken when migrated to newer software versions, due to the unexpected addition of this required conduit. Resolution To fix this problem in Quartus@ Prime Pro software version 25.3.1, install patch 1.23 below for the correct OS (Operating System) Readme: quartus-25.3.1-1.23-readme.txt Linux: quartus-25.3.1-1.23-linux.run Windows: quartus-25.3.1-1.23-windows.exe This problem is scheduled to be fixed in a future release of the Quartus@ Prime Pro Software.Which Protocols Support Spread Spectrum Clocking (SSC) in Agilex® 7 FPGA Devices?
Description In the Agilex® 7 FPGA device family, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using FGT transceivers in F-tile, SSC is enabled by selecting the “Enable Spread Spectrum Clocking” option, while keeping the “Enable TX FGT PLL fractional mode” option disabled in the F-Tile PMA/FEC Direct PHY IP. Resolution N/AWhy does the MIPI DSI‑2 FPGA IP design example fail when programming the FPGA on the Agilex® 3 FPGA and SoC C‑Series Development Kit?
Description Due to an issue in Quartus® Prime Pro Edition software version 26.1, users may encounter a failure when programming the FPGA with the .sof file generated by the MIPI DSI‑2 IP Design Example for the Agilex® 3 FPGA and SoC C‑Series Development Kit. This issue occurs because the design example generation script incorrectly maps the selected Agilex 3 development kit to an unintended target board. When configuring the FPGA using the Quartus Programmer, the following error may be reported: Error(18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0xXX Additionally, the FPGA part number shown in the generated example design may not match the FPGA device on the selected development kit. Resolution To work around this issue in Quartus® Prime Pro Edition software version 26.1, follow the steps below to generate the MIPI DSI‑2 IP Design Example for the correct Agilex® 3 FPGA device. 1. Open the Design Example Tab In the Quartus Prime Pro Edition software, open the MIPI DSI‑2 IP. Navigate to the Parameters window and ensure that the Design Example tab is selected at the top of the MIPI DSI‑2 IP GUI. 2. Select the Correct Target Board In the Target Development Kit section, open the Select Board drop‑down menu and choose the option that corresponds to your development kit, as shown in the table below: Development Kit Kit Part Number FPGA Part Number Target Board Option to Select Agilex® 3 FPGA and SoC C‑Series Development Kit DK‑A3W135BM16AEA A3CW135BM16AE6S Agilex® 3 FPGA C‑Series Development Kit Agilex® 3 FPGA C‑Series Development Kit DK‑A3Y135BM16AEA A3CY135BM16AE6S Agilex® 3 SoC C‑Series Development Kit Ensure that the selected target board option matches your development kit. 3. Generate the Design Example After selecting the correct target board option, click Generate Example Design and allow Quartus to complete the generation process. 4. Verify the FPGA Device Open the generated Quartus project and locate the device OPN in the Project Navigator. Verify that the device OPN (for example, A3CW135BM16AE6S) matches the FPGA part number listed for your development kit in the table above. If the device OPN matches, the design example has been generated correctly and can be programmed onto the FPGA. This problem affects only the target board selection mapping during design example generation for the Agilex® 3 FPGA and SoC C‑Series Development Kit. The MIPI DSI‑2 IP core and generated design examples are otherwise fully functional. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY
Description Due to a problem in the Quartus® Prime Pro edition software version 26.1 and earlier, you may see this problem when using Synopsys VCS* or VCSMX* simulators to simulate the PIO with MCDMA Bypass Mode example design of F-tile Multichannel DMA IP for PCI Express* in Native Endpoint port mode and Multichannel DMA user mode with either AVMM or AVST interface for MCDMA settings. Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Resolution No workaround is available. This issue will be fixed in a future release of Quartus® Prime Pro edition software.Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock?
Description Due to a limitation in the Quartus® Prime Pro Edition Software, the F-Tile Ethernet FPGA Hard IP shows an error when PTP enabled design is connected to system PLL 1 clock. This problem is seen in designs that have multiple IPs and when the IP with PTP enabled is connected to System PLL 1 clock or System PLL2 clock. Resolution The workaround for this limitation is to connect PTP enabled F-Tile Ethernet FPGA Hard IP to System PLL0 clock only.Why can’t the Agilex® 5 FPGA E‑Series 065B Modular Development Kit be configured using the configuration file generated from the GTS AXI Streaming IP for PCI Express* design example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 with the Agilex® 5 FPGA E‑Series 065B Modular Development Kit (Production) MK‑A5E065AB32AEA development kit preset in the GTS AXI Streaming IP for PCI Express, you may see the following error messages when configuring the development kit using a programming file generated from the PCIe design example using that preset. Error(18939): Unexpected error in JTAG server: Internal error Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(18947): Device not responding Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(209012): Operation failed Resolution To work around this problem, replace the following settings in pcie_ed.qsf file of the GTS AXI Streaming IP for PCI Express Design Example set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO16 set_global_assignment -name USE_CONF_DONE SDM_IO12 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name USE_INIT_DONE SDM_IO10 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1 set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF with the following settings set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_125MHZ After that, recompile the design to generate a new programming file. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
Why does the BAM (Bursting Avalon‑MM Master) module of the GTS AXI Multichannel DMA IP for PCI Express* fail to generate Completion TLPs in a PCIe Root Port implementation?
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1, the BAM in the AXI Multichannel DMA IP for PCI Express* may fail to return Completion TLPs in simulation once the completion buffer reaches a specific threshold. In hardware, this problem may manifest as data corruption when the outstanding completion data reaches the same threshold. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do the Configuration Intercept Interface, Control Shadow Interface, Configuration Extension Bus Interface, and VirtIO features not operate as expected when Configuration via Protocol is enabled in the GTS AXI Streaming IP for PCI Express*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 and earlier, enabling the Configuration via Protocol (CvP) feature in the GTS AXI Streaming IP for PCI Express* automatically disables the Configuration Intercept feature within the IP. As a result, all features that rely on the Configuration Intercept Interface, or that internally utilize it, are also affected. Consequently, Vendor‑Specific Extended Capabilities (VSEC) implemented through the Configuration Extension Bus (CEB) Interface cannot be discovered during PCIe enumeration, VirtIO capabilities are not enumerated, and the Control Shadow Interface does not output configuration information as expected. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Which Protocols Support Spread Spectrum Clocking (SSC) on Agilex® 5 and Agilex® 3 FPGA Devices?
Description In the Agilex® 5 and Agilex® 3 FPGA device families, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort Hard Processor System (HPS) USB 3.1 Gen1 SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using GTS transceivers, SSC is enabled by setting the "Spread Spectrum" option to "ENABLE", while keeping the “Enable TX FGT PLL fractional mode” option disabled in the GTS PMA/FEC Direct PHY IP. Resolution N/A
