Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.Why does Aldec Riviera-PRO simulation fail/hang using the PHY Lite for Parallel Interfaces Intel® FPGA IP design example?
Description If PHY Lite for Parallel Interfaces Intel® FPGA IP design example is generated using the Intel® Quartus® Prime Pro Edition Software version 21.1 or 21.2, you will encounter the Aldec Riviera-Pro simulation hang or fail to simulate. This problem was root caused in the Aldec Riviera-Pro version 2020.04, which the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 generates simulation files for. Resolution This problem has been resolved in Aldec Riviera-PRO version 2021.4, which is supported in the Intel® Quartus® Prime Pro Edition Software version 21.3 and onwards. Regenerate your design with the updated Intel Quartus software version.Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.When using the Intel Agilex® 7 FPGA P-Tile, why are simulation errors seen when compiling the Multi-Channel DMA Intel® FPGA IP for PCI Express testbench in the Cadence Xcelium simulator?
Description As stated in Table 34. Supported Simulators for MCDMA IP P-Tile of the Multi-Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide, the Cadence Xcelium simulator is not supported if the simulation of this IP configuration is attempted using Cadence Xcelium, the following error will be seen: $>./xcelium_setup.sh ~~~~~ xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics. xmelab: *F,CUMSTS: Timescale directive missing on one or more modules. xmsim: 20.03-s005: (c) Copyright 1995-2020 Cadence Design Systems, Inc. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries. Resolution Support for the Cadence Xcelium simulator of this IP configuration is planned for a future release of the Intel® Quartus® Prime Pro Edition Software. To work around this problem with the existing IP release, please ensure a supported simulator is used.Why does the design example generation fail when upgrading from Intel® Quartus® Prime Software v21.3 and earlier to v21.4 of the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express?
Description Due to a known problem, the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example generation will fail if the base IP has been upgraded from Intel® Quartus® Quartus Prime Software v21.3 and earlier to v1.4. Resolution When using version 21.4 of the Intel® Quartus® Prime Pro Edition Software, a clean non-upgraded version of the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP must be used. This problem has been fixed starting with the 22.1 version of the Intel® Quartus® Prime Pro Edition Software.A problem with the F-Tile Ethernet Multirate IP in the Quartus® Prime Pro Edition software version 25.3 and earlier for 2x50GE-1 port P2 in UMR3 Dynamic Reconfiguration (DR) group (100G-4 PTP) may result in PTP accuracy error exceeding 8 ns.
Description Due to a problem with the F-Tile Ethernet Multirate IP in the Quartus® Prime Pro Edition software version 25.3 and earlier, PTP may fail to meet the 8 ns accuracy requirement, specifically at the 2x50GE-1. This problem is limited to the 2x50GE-1 rate second port P2; Additionally, the F-Tile Ethernet Multirate IP does not exhibit PTP problems for rates other than 2x50GE-1. As a result of the problem described above, you may experience a similar problem in the F-Tile Dynamic Reconfiguration Suite IP available Example Design when selecting the following options from the GUI under the available Example Designs tab: (1) setting the protocol/mode to Ethernet, and (2) choosing the base variant 100G-4 PTP as shown in Table 10 of section section 3.1.2. Specifically, the example design for implementing 100G-4 PTP to 2x50G-1 PTP does not meet the specifications outlined in the F-Tile Ethernet IP User Guide, resulting in PTP accuracy errors for 2x50G-1 PTP. Other configurations within the same design are unaffected. Below are failure signatures in the Quartus® Prime Pro Edition software version 25.3. ------------------------------ Comparison #1 ------------------------------ RX_ITS - TX_ETS : 0xffffffffc7b07c00/-14415.5156 ns TX Timestamp Fields : 0x3031323334353637BBCC RX Timestamp Fields : 0x3031323334353637BBCC TX Correction Fields : 0x16AA18191A1B1C1D RX Correction Fields : 0x16AA18191A1B1C1D ERROR: PTP Failed ---------------- Done for 50G mode---------------- Resolution As a workaround for this problem, it is recommended not to use 2x50G-1 for 2-port configurations when PTP is enabled in the F-Tile Ethernet Multirate IP in the Quartus® Prime Pro Edition software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why do I see Support-Logic Generation error when implementing the F-Tile Ethernet Intel® FPGA Hard IP with '50GE-2', 'MII PCS only' and 'None" FEC mode options selected ?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, you may see a Support-Logic Generation error when implementing F-Tile Ethernet Intel FPGA Hard IP with '50GE-2', 'MII PCS only' and 'None" FEC mode options selected. The Intel® Quartus® Prime Pro Edition Software versions 21.4 and earlier are not affected. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.2.Why is higher than expected jitter observed when using the SD-SDI video standard with the F-Tile SDI II Intel® FPGA IP parallel loopback with external VCXO Design Example?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the F-Tile SDI II Intel® FPGA IP parallel loopback with external VCXO Design Example has higher jitter than required by the SD-SDI video standard due to the FVH sync signal output from the SDI RX core not being an acceptable source to clock the external VCXO on the daughter card required to synchronize the clock between TX and RX. This problem impacts triple-rate and multi-rate SDI video standard, as SD-SDI is part of the supported standard. This problem will also impact any Intel Agilex® 7 FPGA designs that follow this Intel implementation of the VCXO with TI LMH1983 chip in their design. Resolution To work around this problem, use one of two possible solutions: 1. Use F-Tile SDI II Intel® FPGA IP parallel loopback without external VCXO Design Example. This design supports triple-rate and multi-rate SDI video standard (including SD-SDI), while using internal PLL to synchronize the clock between TX and RX. 2. Use an external sync clock separator chip such as the TI LMH1981, to generate the FVH timing signal and feed the signals to the external VCXO (TI LMH1983) as shown in Figure 1. The TI LMH1981 external clock separator is available on the Nextera and Terasic 12G SDI-FMC daughter card and user has to supply the genlock input to the TI LMH1981 accordingly. Figure 1.Why are packet counters rolling over within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, the packet counters within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP will roll over when small back-to-back packets are encountered, and the packet counters are nearing the saturated value (i.e., all F’s). Resolution There is no workaround for this problem. This problem has been fixed in version 23.2 of the Intel® Quartus® Prime Pro Edition Software.
