Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.
Why does the Synopsys VCS* simulator produce simulation errors with the F-Tile Ethernet Hard IP example design ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may see the following simulation errors with the F-Tile Ethernet Hard IP example design. ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd0, ReaddataValid = 1, Readdata = 01010142, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd4, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fd8, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; ====>IP_INST[ 0] Error!! MISMATCH! Read addr = 007fdc, ReaddataValid = 1, Readdata = 01010101, Expected_Readdata = 00000000; The readdata values of these cwbin counter registers are expected values. The errors are due to wrong check tasks in testbench. Resolution Users can safely ignore these mismatching errors. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz.
Description You may see the following error when entering 805.664062 MHz into the GTS System PLL Clocks IP "Output frequency C0" field, to match the frequency requirement in the GTS Ethernet Hard IP when configured for 25G-1 Ethernet on Agilex TM 5 FPGA devices using the Quartus® Prime Pro software version 25.3.1 and earlier. Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz. Error: <filename>.intel_systemclk_gts_0: "Refclk frequency" (refclk_xcvr_freq_mhz_0) "156.250000" is out of range: "33.109482", "44.145976", "57.547433", "66.218964", "88.291952", "99.328446", "110.364940", "115.094866", "132.437928", "154.510916", "165.547410", "172.642299", "176.583904", "198.656892", "220.729880", "230.189732", "231.766374", "242.802868", "264.875856", "286.948844", "287.737165", "297.985338", "309.021832", "331.094820", "345.284598", "353.167808", "364.204302" This problem is caused by the truncated display of the System PLL frequency in the GTS Ethernet Hard IP. Resolution To work around this problem you can enter 805.6640625 MHz into the “Output frequency C0" field of the GTS System PLL Clocks IP. This problem may be fixed in a future version of the Quartus® Prime Pro software.Why does an error occur when upgrading Ethernet designs that use F‑Tile Ethernet Hard IP from Quartus® Prime Pro Edition version 22.4 or earlier to version 25.3.1?
Description Due to an issue in Quartus® Prime Pro Edition software version 22.4 and earlier, an error may be encountered when upgrading Ethernet designs created with F‑Tile Ethernet Hard IP to version 25.3.1. Error: ex_100G.eth_f_0: "Custom Ethernet line rate" (CUSTOM_RATE_GUI) 25.78125 is out of range: 10.3125-17.4 This problem is observed because the maximum supported line rate for the “Custom Ethernet line rate” was incorrectly changed to 17.4 Gbps. Resolution One workaround using the F‑Tile Ethernet Hard IP GUI is to open the .ip file, change the Ethernet mode to a different data rate, and then reconfigure it back to the original data rate. Alternatively, edit the .ip file directly by locating CUSTOM_RATE_GUI and changing its value from 25.78125 to 10.3125 Gbps. This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.What Agilex™ 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe* REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Agilex™ 7 FPGA Device Configuration via Protocol (CvP) Implementation User Guide Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why does the Arria® 10 HDMI FPGA IP Design Example polarity inversion setting not affect the generated RTL?
Description Due to a problem in the Arria® 10 FPGA HDMI FPGA IP Design Example when using the Quartus® Prime Pro Edition Software version 23.4, the polarity inversion setting for the HDMI RX PHY does not affect the generated RTL. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 23.4. Download and install Patch 0.63 below. Step to enable polarity inversion: Apply patch Generate design example Edit ./rtl/ip/nios/intel_hdmi_rx_phy.ip in the IP GUI and set parameters based on user requirement regenerate the IP by clicking "generate HDL" Compile the design Run in the hardware This problem is fixed beginning with version 25.1 of the Quartus® Prime Pro Edition Software.Why are the R-Tile AXI Multichannel DMA IP Design Example DMA Queues stuck when the Gen5 IP configuration links downgrade to Gen4 or lower speeds?
Description Due to a problem in the Quartus® Prime Pro software version 25.3.1 and earlier, the AXI Multichannel DMA IP Queues will stick if the Gen5 configuration of the IP is link downgrades to Gen4 or lower. For example in the Gen5 IP is used in a Gen4 system. Resolution To fix this problem in Quartus® Prime Pro software version 25.3.1 please install patch 1.01 below. This problem is scheduled to be fix in a future release of the Quartus® Prime Pro software. IP Core AXI Multichannel DMA IP for PCI Express*Why do I see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled in the Quartus® Prime Pro Edition software version 25.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled. This is because the Firecode FEC isn’t supported in F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1.Why doesn’t the CDR lock signal assert in simulation for some F Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition in the Quartus® Prime Pro Edition software version 25.3.1?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see simulation failure that CDR lock signal doesn’t assert for some F‑Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition. Resolution There is no workaround currently. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro edition software.Why does the F-Tile JESD204C FPGA IP Example Design fail to generate when the data rate above 23 Gbps with a target development kit selected, showing an error requiring VSR_MODE_HIGH_LOSS even though this option is unavailable in the IP GUI?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, the VSR_MODE_HIGH_LOSS option was removed. User is expected to use VSR_MODE_LOW_LOSS instead, which provides the same functionality previously available in both modes. However, this change is not correctly reflected in the F-Tile JESD204C IP GUI. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.3, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1.