Why does the start_basic_test procedure fail when running the GTS JESD204B FPGA IP Design Example on the Agilex™ 5 FPGA hardware?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you may observe intermittent failures when running the start_basic_test procedure with the GTS JESD204B FPGA IP Design Example. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.3, download and install the patch below. After installing the patch, do the following: Depending on the data rate, configure the IP ➤ Analog Parameters ➤ Analog Rx ➤ RX Adaptation mode: Manual: if data rate <= 7Gbps Auto: if data rate > 7Gbps Regenerate the design example. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Why am I seeing some packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, 25.3 and 25.3.1, you may see traffic failures with packet drop/loss when using the F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled 100G designs. Resolution Add the solution or the workaround to fix the problem or bug. Additional Information Currently there is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why o_rx_pcs_fully_aligned does not assert for 40GE-4 Advanced mode F-Tile Ethernet Hard IP design when Custom Ethernet line rate > 63Gbps?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, you might observe o_rx_pcs_fully_aligned does not assert for the F-Tile Ethernet Hard IP design with below configurations: Advanced mode: Enabled Ethernet mode: 40GE-4 Custom Ethernet line rate: > 63 Gbps Resolution There is no workaround. There is no fix planned in the future. When advanced mode enabled for 40GE-4 design, supported custom Ethernet line rate is: 41.25~63 Gbps.Why does the GTS SDI II IP Multi-rate Serial Loopback Design Example fail to achieve lock on Agilex™ 5 FPGA E-Series Modular Development Kit at 12G data rate?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may observe the rx_align, rx_frame and rx_trs signals fail to achieve lock when running the GTS SDI II IP Multi-rate Serial Loopback Design Example on Agilex™ 5 FPGA E-Series Modular Development Kit at 12G data rate. Resolution There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the Design Closure Summary fail in the Agilex™ 5 FPGA and Agilex™ 7 FPGA HDMI IP Example Designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may observe the Design Assistant Summary flagged with High Severity Violations and Design Closure Summary marked as Fail in the Agilex™ 5 FPGA and Agilex™ 7 FPGA HDMI IP Example Designs. These warnings can be safely ignored. Resolution There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does internal serial loopback test results fail when running the GTS JESD204B FPGA IP Design Example on Agilex™ 3 FPGA or Agilex™ 5 FPGA hardware?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter a failed test result when running the internal serial loopback test with the GTS JESD204B FPGA IP Design Example. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.3, download and install patch below. After installing the patch, do the following: In the GTS JESD204B IP GUI editor, IP > Main tab, enabled the following checkboxes: Enable PMA Avalon memory-mapped interface Enable control and status registers Depending on the data rate, configure the IP ➤ Analog Parameters ➤ Analog Rx ➤RX Adaptation mode: Manual: if data rate <= 7Gbps Auto: if data rate > 7Gbps Regenerate the design example. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Why am I seeing Deterministic Latency Accuracy problems when using Inter-protocol Designs in the GTS Dynamic Reconfiguration Controller IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and earlier, you may inter-protocol GTS Ethernet Hard IP with PTP and GTS CPRI IP in GTS Dynamic Reconfiguration Controller IP designs. Resolution Currently, there is no workaround for this problem. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software. Related IP Core GTS Dynamic Reconfiguration Controller IP GTS Ethernet Hard IP with PTP GTS CPRI IPWhy does my PCIe* Independent GPIO PERST# test design fail to compile when I target the GXF_2ND_PERSTn signal on Pin CN11 of the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023)?
Description Due to a mistake on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), the PCIe* Independent GPIO PERST# is shown going to two Pin locations: GXF_2ND_PERSTn signal on Pin CN11 on Sheet 22 should be DNU (Do Not Use). GXF_1V2_2ND_PERSTn signal on Pin B46 on Sheet 16 is a valid GPIO on Bank 3A, and this should be used. Resolution When testing Independent GPIO PERST# in Bifurcated 2x8 Mode on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023), either test in Single PERST# Mode when both x8 Cores are connected to the same host, or use Pin B46, which is a valid GPIO in Bank 3A. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi-Channel DMA FPGA IP for PCI Express*
Why does the Agilex™3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, fail during simulation using Xcelium* and Riviera*-PRO simulators in Quartus® Prime Pro Edition Software version 25.1.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, the Agilex™ 3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, may fail during simulation of the design example testbench. The following behaviors may be observed: Riviera*-PRO: Simulation may hang or display "Error: Accuracy criteria not met". Xcelium*: Simulation may pass, but accuracy criteria will not be met, leading to incorrect results. Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software Version 25.1.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the GTS JESD204B/C FPGA IP and Design Example generation fail on Agilex™ 3 FPGA and Agilex™ 5 FPGA devices when selecting System or HVIO PLL clocking mode?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter an error message like the following when generating the GTS JESD204B/C FPGA IP Design Example. "Error: phy_inst.inst_directphy: System/HVIO PLL frequency "307.2" cannot be smaller than transceiver's parallel clock frequency "858.0" The following IP configuration steps may lead to the above error: Set the Data rate to a specific value Set the Datapath clocking mode System PLL Enable the example design generation Enable Simulation and/or Synthesis in the Example Design Files section Increase the data rate to a value higher than the data rate set in step 1 Generate the IP or Example Design *Note that this problem will not occur when you use a data rate set in Step 5 lower than the data rate set in Step 1. Resolution When you encounter this error, use the following workaround: Disable example design generation Update the System PLL frequency for the latest data rate Enable example design generation Generate the IP or Example Design This problem will be fixed in a future release of the Quartus Prime Pro Edition Software.