Why does the example design fail to generate when "Dual Simplex Applied on JESD204B PHY" is selected with "Enable Manual F" enabled and the F value greater than 4?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1, you may observe the Dual Simplex (DS) PHY wrapper example design for GTS JESD204B IP fails to generate when the JESD204B DS Wrapper option is used with "Dual Simplex applied on JESD204B PHY" selected in the IP GUI, "Enable Manual F" is enabled, and the F value is set greater than 4. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition version 25.3.1.When using the R-Tile Avalon Streaming IP for PCI Express* how should the CPL Always Grant option be used?
Description CPL Always Grant is a new option in the GUI for the R-Tile Avalon Streaming IP for PCI Express. If the parameter is turned on, internally generated TLPs (completion and message) will check for available credits at the link partner (i.e., total credit) and will not be limited to the locally allocated credit of 1, 4, or 16, depending on the scale factor used. If the parameter is turned off, which is the default: Consider that there are 100 completion credits available and we allocated 4 credits for internally generated completions. After 4 config reads are received and after the Hard IP has sent 4 completions in response, the 5th config read received will not result in a completion being transmitted by the Hard IP until a credit update is received from the Root Port, even though the Hard IP still has 96 credits available for completions. This behaviour applies only to configuration requests which require completions to be generated by the PCIe Hard IP. Internally generated messages are posted and do not require completions to be generated. The FC_Update check is not bypassed when the CPL Always Grant option is turned on. The Hard IP keeps track of available credits at the link partner and prevents any TLPs (internal or user- generated) from being transmitted through the link enough credits are not available. For header and data, the credits reserved for internal IP usage are 1, 4, and 16 for scaling factors of 1, 4, and 16 respectively. Header credits and data credits have their own allocation. For new designs targeting an interoperable vendor-neutral system architecture, Altera recommends that this option be enabled. Resolution This information is scheduled to be included in a future release of the R-Tile Avalon Streaming IP for PCI Express User Guide.Why do the Resource Utilization results remain the same for the Agilex® 3 GTS JESD204B IP Core with either ECC_EN On or Off?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you may observe the resource utilization results remain the same in Agilex® 3 GTS JESD204B IP core with either ECC_EN On or Off Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition version 25.1.1.Does the Agilex® 7 FPGA F-Series (2 × F-Tiles) Development Kit support CvP over the PCIe* 4.0x16 Gold Fingers?
Description The Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023) do not support CvP over the PCIe* 4.0x16 Gold Finger Card Edge connector. CvP is supported over the MCIO x4 interface. Resolution CvP is not supported over the PCIe* 4.0x16 Gold Finer Card Edge Connector on the Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023). This problem will not be fixed in a future release as the problem is due to the physical location of the PCIe* 4.0x16 F-Tile being located on the Right Hand Side of the device. CvP is only supported on the Left Had Side Tile of this device.
Why is the FPGA To HPS bridge not functional in a non-HPS EMIF hardware design in Agilex® 5 FPGA device in 25.3.1 release and earlier?
Description Due to an incorrect configuration in the mpfe_config register in the System Manager, performed by the SDM FW, the FPGA-to-HPS transactions will fail to complete on the Agilex® 5 FPGA device in a hardware design that does not instantiate the HPS EMIF IP created with Quartus® Prime 25.3.1 and before. The problem resides in the incorrect value that the SDM FW assigns to the mpfe_config[f2soc_intfcsel] bit when the HPS EMIF is not instantiated. Under this scenario, it is expected that the f2soc_intfcsel field has a value of ‘1', but this is set to '0’ instead. Resolution To workaround this problem, you can set the mpfe_config[f2soc_intfcsel] bit to '1' in the FSBL. The following snippet shows an example of how to do it in U-Boot SPL: #define MPFE_CONFIG_F2SOC_INTFCSEL_BIT 0 void board_init_f(ulong dummy) { : setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(MPFE_CONFIG_F2SOC_INTFCSEL_BIT)); do_bridge_reset(1, RSTMGR_BRGMODRST_FPGA2SOC_MASK ); : } This needs to be done before the FPGA-to-HPS (F2H) bridge is released from reset. This problem will be fixed in a future release. Note: If your non-HPS EMIF design instantiates the Altera ACE5-Lite Cache Coherency Translator (CCT) and, after applying the above workaround, you observe that read transactions in the FPGA-to-HPS (F2H) bridge succeed, but after a write transaction, the system hangs, you may require an additional fix in the ACCT IP that will be released together with the mpfe_config[f2soc_intfcsel] configuration fix. Please refer to Why does the Agilex® 5 FPGA Hard Processor System hang during ACCT IP operations when translating AXI4 to ACE5‑LITE?What Agilex® 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe® REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Resolution This information has been scheduled for inclusion in the next release of the Agilex® PCI Express* IP User Guides. Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why does Quartus® Prime Pro Edition version 25.1.1 and later add a phased_clk_lock_interface conduit to the altera_eth_1588_tod IP when targeting Agilex® 7 FPGA devices?
Description In Quartus® Prime Pro Edition software version 25.1.1 and later, when targeting Agilex® 7 FPGA devices, the altera_eth_1588_tod IP exposes an additional phased_clk_lock_interface conduit. This interface conduit was not present in earlier Quartus® Prime Pro Edition versions. As a result, designs that were originally created and validated using Quartus® Prime Pro Edition version 25.1 or earlier may encounter connectivity issues or appear broken when migrated to newer software versions, due to the unexpected addition of this required conduit. Resolution To fix this problem in Quartus@ Prime Pro software version 25.3.1, install patch 1.23 below for the correct OS (Operating System) Readme: quartus-25.3.1-1.23-readme.txt Linux: quartus-25.3.1-1.23-linux.run Windows: quartus-25.3.1-1.23-windows.exe This problem is scheduled to be fixed in a future release of the Quartus@ Prime Pro Software.Which Protocols Support Spread Spectrum Clocking (SSC) in Agilex® 7 FPGA Devices?
Description In the Agilex® 7 FPGA device family, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using FGT transceivers in F-tile, SSC is enabled by selecting the “Enable Spread Spectrum Clocking” option, while keeping the “Enable TX FGT PLL fractional mode” option disabled in the F-Tile PMA/FEC Direct PHY IP. Resolution N/AWhy does the MIPI DSI‑2 FPGA IP design example fail when programming the FPGA on the Agilex® 3 FPGA and SoC C‑Series Development Kit?
Description Due to an issue in Quartus® Prime Pro Edition software version 26.1, users may encounter a failure when programming the FPGA with the .sof file generated by the MIPI DSI‑2 IP Design Example for the Agilex® 3 FPGA and SoC C‑Series Development Kit. This issue occurs because the design example generation script incorrectly maps the selected Agilex 3 development kit to an unintended target board. When configuring the FPGA using the Quartus Programmer, the following error may be reported: Error(18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0xXX Additionally, the FPGA part number shown in the generated example design may not match the FPGA device on the selected development kit. Resolution To work around this issue in Quartus® Prime Pro Edition software version 26.1, follow the steps below to generate the MIPI DSI‑2 IP Design Example for the correct Agilex® 3 FPGA device. 1. Open the Design Example Tab In the Quartus Prime Pro Edition software, open the MIPI DSI‑2 IP. Navigate to the Parameters window and ensure that the Design Example tab is selected at the top of the MIPI DSI‑2 IP GUI. 2. Select the Correct Target Board In the Target Development Kit section, open the Select Board drop‑down menu and choose the option that corresponds to your development kit, as shown in the table below: Development Kit Kit Part Number FPGA Part Number Target Board Option to Select Agilex® 3 FPGA and SoC C‑Series Development Kit DK‑A3W135BM16AEA A3CW135BM16AE6S Agilex® 3 FPGA C‑Series Development Kit Agilex® 3 FPGA C‑Series Development Kit DK‑A3Y135BM16AEA A3CY135BM16AE6S Agilex® 3 SoC C‑Series Development Kit Ensure that the selected target board option matches your development kit. 3. Generate the Design Example After selecting the correct target board option, click Generate Example Design and allow Quartus to complete the generation process. 4. Verify the FPGA Device Open the generated Quartus project and locate the device OPN in the Project Navigator. Verify that the device OPN (for example, A3CW135BM16AE6S) matches the FPGA part number listed for your development kit in the table above. If the device OPN matches, the design example has been generated correctly and can be programmed onto the FPGA. This problem affects only the target board selection mapping during design example generation for the Agilex® 3 FPGA and SoC C‑Series Development Kit. The MIPI DSI‑2 IP core and generated design examples are otherwise fully functional. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY
Description Due to a problem in the Quartus® Prime Pro edition software version 26.1 and earlier, you may see this problem when using Synopsys VCS* or VCSMX* simulators to simulate the PIO with MCDMA Bypass Mode example design of F-tile Multichannel DMA IP for PCI Express* in Native Endpoint port mode and Multichannel DMA user mode with either AVMM or AVST interface for MCDMA settings. Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Resolution No workaround is available. This issue will be fixed in a future release of Quartus® Prime Pro edition software.
