Why are there errors while generating an example design using GTS Transceiver with Dynamic Reconfiguration (DR) between two rates in the Quartus® Prime Pro Edition software version 25.1?
Description Performing DR between two rates using the GTS Transceiver was throwing an error when using manual adaptation mode during example design generation. The errors reported in the IP Catalog GUI during the generation process appear due to the in-built functionality of adaptation mode being set to disabled in the simulation. Due to the disabled adaptation mode, any non-zero values for RX PMA analog parameters in simulation mode throw an error. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.1, set RX PMA analog parameters in the IP Catalog GUI to 0. This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.1.1.Why is the link-up failure observed for the F-tile Dynamic Reconfiguration Suite IP with Auto-Negotiation and Link Training (AN/LT) enabled designs when trying to skip Link Training (LT)?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3.1, you may see the link-up failure for the F-tile Dynamic Reconfiguration Suite IP with Auto-Negotiation and Link Training (AN/LT) enabled designs when trying to skip Link Training (LT). Resolution Currently, there is no workaround for this problem. The ideal user flow is as follows: AN --> AN done --> perform DR --> DR done --> start LT --> LT done --> data mode+send traffic This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.1.1.Why is my hardware test failing when using GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) and ECC enabled?
Description Due to a problem in the GTS Ethernet Hard IP in the Quartus® Prime Pro Edition software version 25.1, designs with Auto-Negotiation and Link Training (AN/LT) and ECC enabled may experience hardware failure. When ECC is enabled in AN/LT designs, it shows a critical warning during the qsys stage, which prevents hex/mif from being loaded in the fitter stage, causing the hardware to fail. Resolution To work around this problem, copy the imem and dmem hex files from “/intel_eth_gts_0_example_design/hardware_test_design/common/intel_eth_anlt_gts_0/intel_eth_anlt_gts_301/synth” folder to “/intel_eth_gts_0_example_design/hardware_test_design/” folder. This will resolve the problem. This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.1.1.Why are HVIO pins not having the optional function SYSPLLREFCLK allowed to be assigned as a reference clock for the System PLL for the Agilex® 3 FPGA and Agilex® 5 FPGA GTS transceiver in the Quartus® Prime Pro Edition software version 25.1 and earlier?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1 and earlier, it incorrectly allows the assignment of other HVIO pins without the SYSPLLREFCLK description. An example of a correct selection would be the HVIO pin with the following optional functions listed: HVIO_5B_1, SYSPLLREFCLK_L1A_0, TXCLK1, Data_Ctrl1. This is the correct pin to select as a reference clock for the system PLL in the GTS transceiver bank 1A. An example of an incorrect selection would be an HVIO pin without the SYSPLLREFCLK optional function listing: HVIO_5B_20, TXCLK20, Data_Ctrl20. Therefore, selecting this as a reference clock pin for system PLL is incorrect, but the Quartus® Prime Pro Edition software does not currently report this as an error. Resolution To work around this problem, refer to the device pinout and pin connection guidelines and ensure it has the correct SYSPLLREFCLK optional function when selecting an HVIO pin as a system PLL reference clock. Agilex® 5 FPGA Device Pin-out Files Agilex® 5 FPGA Pin Connection Guidelines This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.Why does Quartus® Prime Pro compilation fail with error 23051 after upgrading the F-Tile HDMI IP Design Example to 25.1.1?
Description The F-Tile HDMI Altera® Design Example in Quartus® Prime Pro Edition Software 25.1.1 compilation fails at the Logic Generation stage, and Quartus® reports an error of the following form: Error(23051): NIOS data memory size 1024KBytes of Dynamic Reconfiguration Controller IP agx_hdmi21_frl_axi_demo/u_nios/dr_f/nios_dr_f is smaller than required MIF Size of 1141464Bytes to store the data in NIOS Memory This error also occurs after upgrading the F-Tile HDMI Altera® Design Example from previous versions. This is due to a significant memory increase in the MIF size required by the F-Tile Dynamic Reconfiguration (DR) IP. Resolution Increase the DR memory size in Quartus® Prime Pro Edition Software 25.1.1 to overcome the compilation error. A new memory size option is introduced in the Nios® data memory size within the Dynamic Reconfiguration IP GUI, which allows memory size selection up to 2048kB. i.e., double the maximum amount of memory previously. In the HDMI Design in Quartus, under Project Navigator, navigate to the IP Components tab and open nios_dr_f to launch the F-Tile Dynamic Reconfiguration Suite IP GUI. In the Dynamic Reconfiguration Controller IP tab ➤ Select NIOS data memory size option as 2048KBytes. Regenerate the DR IP by clicking on Generate HDL to regenerate the HDL files required. Recompile the design. #NOTE There will be an increase in M20K memory blocks in your chosen device when choosing this option Additional Information The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Why does the HDMI Design Example fail to generate when using the Quartus® Prime Standard Edition Software version 24.1?
Description From Quartus® Prime Standard Edition Software version 24.1 onwards, Nios® II has been removed and is now End-of-Life (EOL). The HDMI Design Example hasn't been upgraded to Nios® V yet, and so this causes the design example generation to fail. The error below will be seen when trying to generate the design example for the listed device families: "Error: Failed to generate example design example_design to: " Resolution No workaround for this problem exists. If necessary, use the Quartus® Prime Standard Edition Software version 23.1 until this problem is resolved in a future release. Additional Information This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the GTS JESD204B/C FPGA IP and Design Example generation fail on Agilex® 3 FPGA and Agilex® 5 FPGA devices when selecting System or HVIO PLL clocking mode?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter an error message like the following when generating the GTS JESD204B/C FPGA IP Design Example. Error: phy_inst.inst_directphy: System/HVIO PLL frequency "307.2" cannot be smaller than transceiver's parallel clock frequency "858.0 The following IP configuration steps may lead to the above error: Set the Data rate to a specific value Set the Datapath clocking mode System PLL Enable the example design generation Enable Simulation and/or Synthesis in the Example Design Files section Increase the data rate to a value higher than the data rate set in step 1 Generate the IP or Example Design *Note that this problem will not occur when you use a data rate set in Step 5 lower than the data rate set in Step 1. Resolution When you encounter this error, use the following workaround: Disable example design generation Update the System PLL frequency for the latest data rate Enable example design generation Generate the IP or Example Design The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why am I seeing compilation failure for F-tile Ethernet Hard IP designs for non-MAC variants?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see compilation failure for F-tile Ethernet Hard IP designs for non-MAC variants. This issue happens if the GUI MAC parameters TX VLAN detection, RX VLAN detection, and Average Inter-Packet Gap are changed for non-MAC variants. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.3, set MAC parameter values to the default value (TX VLAN =1, RX VLAN=1, IPG_SIZE=12) for the Non-MAC interface. This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.1.
Why does the GTS AXI Multichannel DMA IP for PCI Express* IP send Completion Data (CplD) with a length exceeding the Maximum Payload Size (MPS) set?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the GTS AXI Multichannel DMA IP for PCI Express* IP sends Completion with Data (CplD) lengths that exceed the negotiated Maximum Payload Size (MPS) set. Resolution Patches are available to fix this problem for the Quartus Prime Pro Edition Software version 26.1 versions. Download and install patch below. Quartus Prime Pro Edition Software v26.1 Patch 0.20 This problem is currently scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does the R-tile AXI Streaming IP for PCI Express* Example Design simulation testbench fail to compile in the Quartus® Prime Pro Edition software version 25.1?
Description Due to a problem in the 25.1 and earlier versions of the R-Tile AXI Streaming IP for PCI Express*, the example design simulation testbench may fail compilation with the following error: Error-[CFCILFBI] Cannot find cell in liblist ./../..//../../ip/pcie_ss_ed_sim_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_100/sim/altpcietb_bfm_rp_gen5_x16_cfbp.sv, 3254 Cell 'pcie_ed_sim_resetIP' cannot be found in liblist for binding instance 'pcie_ss_ed_sim_tb.dut_pcie_tb.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.resetip'. Resolution To work around this problem, navigate to <generated_ed_path>/pcie_ss_ed_sim_tb/ip/pcie_ss_ed_sim_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_100/sim/ and open the file altpcietb_bfm_rp_gen5_x16_cfbp.sv with a text editor. Search for the keyword 'resetIP' for the line where the resetIP module was instantiated, and change the module name from pcie_ed_sim_resetIP to pcie_ss_ed_sim_resetIP. Before: After: Save the file and re-run the simulation scripts. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.
