Which Protocols Support Spread Spectrum Clocking (SSC) on Agilex® 5 and Agilex® 3 FPGA Devices?
Description In the Agilex® 5 and Agilex® 3 FPGA device families, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort Hard Processor System (HPS) USB 3.1 Gen1 SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using GTS transceivers, SSC is enabled by setting the "Spread Spectrum" option to "ENABLE", while keeping the “Enable TX FGT PLL fractional mode” option disabled in the GTS PMA/FEC Direct PHY IP. Resolution N/AError(22650): File <filename>.jic is corrupted. DCIO/Main section data information is not found
Description Due to a bug in Quartus® Prime Pro Edition Software version 25.3.1 or earlier, when using Agilex® 5 FPGA or Agilex® 7 FPGA series devices, you may see this error when examining a JIC file (using quartus_pfg --info or the Configuration Debugger tool) that has been generated where the Direct Factory Image Fallback flag has been enabled on a signed BOOT_INFO .rbf image. This error occurs because this setting needs to be applied before the image is signed.. Resolution A future update of the quartus_pfg flow in the Quartus® Prime Pro Edition Software will include a method to generate .rbf files with the Direct Factory Image Fallback flag set to a user-desired value before encryption and signing.
Why do several IP design examples fail on the Agilex® 7 FPGA Series Transceiver SoC Development Kit?
Description The following IP Cores generate example designs for the Agilex® 7 FPGA Series Transceiver SoC Development Kit with incorrect VID settings. 1) Serial Lite IV IP 2) Interlaken (2nd Generation) IP 3) Triple-Speed Ethernet IP 4) E-Tile Dynamic Reconfiguration IP 5) E-Tile Hard IP for Ethernet and CPRI PHY IP 6) JESD204B IP 7) JESD204C IP 8) Ethernet Subsystem IP Resolution The correct VID settings can be found in section 6.1, Add SmartVID settings in the Quartus® Prime QSF file of the Agilex® F-Series Transceiver-SoC Development Kit User Guide. Update the design examples with the correct VID settings as shown below: set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13" set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.