Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why are UnsupReq, NonFatalErr, and CorrErr statuses asserted after power cycle or OS reboot while using the P-Tile Intel® FPGA IP for PCI Express?
Description You may find UnsupReq, NonFatalErr, and CorrErr status asserted after power cycle or operating system (OS) reboot when using the P-Tile Intel® FPGA IP for PCI Express. Resolution According to the PCI Express Base specification revision 4.0 version 1.0, during the enumeration of a non-existent device or function, completion with UR status is sent, and UnsupReq is asserted. Meanwhile, Non-Fatal Advisory Error is determined, and CorrErr and NonFatalErr are asserted. To work around this problem, clear the UnsupReq, NonFatalErr, and CorrErr statuses in the PCI Express configuration space registers before checking them during data transactions. This problem is not planned to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.Why does the F-Tile Dynamic Reconfiguration Suite Intel® IP Design Example using VHDL fail to simulate correctly when using the Cadence® Xcellium simulator?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the VHDL design example implementation of the F-Tile Dynamic Reconfiguration Suite Intel® IP fails to simulate correctly. The Cadence® Xcellium simulator will generate warnings related to the dr_cpu_ctrl_inst module containing text similar to that shown below: Attempted propagation of defparam results to a non-Verilog instance Resolution To work around this problem in simulation, edit the run_xcelium.sh file to add a new -generic switch to force and set the dr_cpu_ctrl DMEM_INIT_FILE with the correct *_combined mif file generated from QTLG flow. Note: Ensure that the correct mif file name has been used only after the Quartus Support-logic Generation stage has run. An example of the required assignment is shown below: xmelab -relax -timescale '1 ps / 1 ps' -access +rwc -generic "basic_avl_tb_top.eth_f_hw.dr_dut:dr_f_0.dr_cpu_ctrl_inst:DMEM_INIT_FILE => \"eth_f_hw__combined_z1577a_x0_y166_n0.mif\"" basic_avl_tb_top This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" Resolution Workaround: To work around this problem, follow the steps below: Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” Save the updated .ip file. Reopen the modified .ip file in the Quartus® IP Parameter Editor. Depending on your use case, click “Generate Example Design” or “Generate HDL.”Why does the F-Tile JESD204C Altera® IP Design Example fail to compile when migrated from a previous version of the Quartus® Prime Pro Edition Software to version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile JESD204C Altera® IP Design Example will fail to compile when migrated from any previous version of the Quartus® Prime Pro Edition Software to version 24.3. Resolution Follow the instructions below to work around this problem in the Quartus® Prime Pro Edition Software version 24.3 by manually editing the module to remove the unused port. In the Files tab under Project Navigator window, locate the ed_control IP file (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control.ip) . Expand the directory and find the target module (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control/synth/j204c_f_<data path>_ss_ed_control.v) Comment out the all “csr_tst_ctl_tst_control_error_inject” ports. For example: // output wire csr_tst_ctl_tst_control_error_inject The problem has been fixed starting with Quartus® Prime Pro Edition software version 24.3.1.Why does the PHY Lite for Parallel Interfaces for Intel® Arria® 10 FPGA IP fail simulation when the data configuration is set to “Differential”?
Description Due to a problem in the Intel® Quartus® Prime Software version 19.1, you may see simulation read errors when you set the data configuration to “Differential.” Resolution To work around these problems, open the *phylite_io_bufs.sv file under the altera_phylite_arch_nf_*\sim directory. Change the line from: assign group_data_out_n [grp_num][47 : GROUP_PIN_WIDTH[grp_num]-1]={(MAX_WIDTH-GROUP_PIN_WIDTH[grp_num]){1'b0}}; to: assign group_data_out_n [grp_num][47 : GROUP_PIN_WIDTH[grp_num]]={(MAX_WIDTH-GROUP_PIN_WIDTH[grp_num] 1){1'b0}}; This problem is fixed starting with the Intel® Quartus® Prime Software version 19.3.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1
Description You may encounter the below fitter error when designing with the Agilex™ 5 FPGA MIPI D-PHY IP in Quartus® Prime Pro Edition version 24.1 when using a specific reference clock frequency and bit rate combination. Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid, and the Fitter must be restarted. Resolution These errors are caused by an invalid combination of reference clock frequency and operating bit rate. These combinations will be removed in a future release of the Quartus® Prime Pro Edition Software.Error: Execution of command "{/nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Description Due to a problem in the Quartus® Prime Standard Edition Software version 19.1 Windows* version onwards, you might see this error when generating the UniPHY-based External Memory Interface IP. Resolution Install the Windows Subsystem for Linux (WSL) on Windows OS for all Quartus® Prime Standard Edition Software versions 19.1 Windows version onwards. For more details, refer to this article. There is an additional workaround requirement if you are using Quartus® Prime Standard Edition software version 19.1 on Windows. For more details, refer to this article. There is an additional workaround if you use Windows 10 version 19.03 and later. For more details, refer to this article. Related Articles How to install the Windows Subsystem for Linux (WSL) on Windows OS? FATAL: Cannot generate IP in a Windows environment! Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormallyError(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)).
Description The fitter error shown below will be seen when using the Quartus® Prime Pro Edition Software version 24.1 when placing the reference clock pin(s) or RZQ pin in a different sub-bank than the Agilex™ 5 MIPI D-PHY FPGA IP has been placed. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 IOPLL, which is within Generic Component dphy_dut_dphy. Resolution To workaround this problem, please set the reference clock input type to not balanced in your Quartus® Settings File (.qsf). Shown below is an example of the required assignment for the Design Example generated by the Agilex™ 5 MIPI D-PHY FPGA IP. set_instance_assignment -name PLL_REFCLK_INPUT_TYPE NOT_BALANCED -to *dphy_core_inst|clk_rst|pll_gen[*].iopll_wrap_inst|iopll_inst -entity ed_synthError (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s))
Description You may see the errors below in the Quartus® Prime Pro Edition Software version 20.3 when compiling the Agilex™ 3 FPGA PHYLite IP. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 pin, which is within ed_synth ed_synth. Error(16234): No legal location could be found out of 1772 considered location(s). Reasons why each location could not be used are summarized below: Error(175005): Could not find a location with: DQS_x36 (1 location affected) Error(175008): Location was not in the legal region (1771 locations affected) Resolution These errors are due to hardware limitations. A configuration of the Agilex™ 3 FPGA PHYLite IP, where X8/X9 and X32/X36 DQS groups are used simultaneously in the same IO48 sub-bank, is unsupported.