Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.Why is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.A problem with the F-Tile Ethernet Multirate IP in the Quartus® Prime Pro Edition software version 25.3 and earlier for 2x50GE-1 port P2 in UMR3 Dynamic Reconfiguration (DR) group (100G-4 PTP) may result in PTP accuracy error exceeding 8 ns.
Description Due to a problem with the F-Tile Ethernet Multirate IP in the Quartus® Prime Pro Edition software version 25.3 and earlier, PTP may fail to meet the 8 ns accuracy requirement, specifically at the 2x50GE-1. This problem is limited to the 2x50GE-1 rate second port P2; Additionally, the F-Tile Ethernet Multirate IP does not exhibit PTP problems for rates other than 2x50GE-1. As a result of the problem described above, you may experience a similar problem in the F-Tile Dynamic Reconfiguration Suite IP available Example Design when selecting the following options from the GUI under the available Example Designs tab: (1) setting the protocol/mode to Ethernet, and (2) choosing the base variant 100G-4 PTP as shown in Table 10 of section section 3.1.2. Specifically, the example design for implementing 100G-4 PTP to 2x50G-1 PTP does not meet the specifications outlined in the F-Tile Ethernet IP User Guide, resulting in PTP accuracy errors for 2x50G-1 PTP. Other configurations within the same design are unaffected. Below are failure signatures in the Quartus® Prime Pro Edition software version 25.3. ------------------------------ Comparison #1 ------------------------------ RX_ITS - TX_ETS : 0xffffffffc7b07c00/-14415.5156 ns TX Timestamp Fields : 0x3031323334353637BBCC RX Timestamp Fields : 0x3031323334353637BBCC TX Correction Fields : 0x16AA18191A1B1C1D RX Correction Fields : 0x16AA18191A1B1C1D ERROR: PTP Failed ---------------- Done for 50G mode---------------- Resolution As a workaround for this problem, it is recommended not to use 2x50G-1 for 2-port configurations when PTP is enabled in the F-Tile Ethernet Multirate IP in the Quartus® Prime Pro Edition software version 25.3. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.What is the recommended termination guideline for mem_reset_n when using DDR3 SDRAM controller with UniPHY?
Description Altera® does not recommend terminating the mem_reset_n signal. DDR3 DIMMs typically do not use any termination on the memory reset signal. Refer to the memory vendor datasheet for any memory reset termination guidelines. Resolution Related Articles Can I use a USB Blaster download cable for AES key programming? Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller Can I place bonded transceiver channels non-contiguously in Stratix® V and Arria® GZ transceiver devices?Why does compiling the PHY Lite for Parallel Interfaces IP example design for Agilex™ 3 FPGA C-Series and Agilex™ 5 FPGA E-Series and D-Series generate invalid Fitter assignment warnings?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see that the PHY Lite for Parallel Interfaces IP example design compilations for Agilex™ 3 FPGA C-Series and Agilex™ 5 FPGA E-Series and D-Series generate a warning message on invalid Fitter assignments. The following assignments are invalid and listed in the Ignored Assignments panel in the Fitter Compilation Report: Can Relax Periphery to Core Hyper Register Constraint TOP_FEEDBACK_DELAY_STEP TOP_FEEDBACK_DELAY_SEL BOT_FEEDBACK_DELAY_STEP BOT_FEEDBACK_DELAY_SEL Resolution There is no workaround for this problem in the Quartus® Prime Pro Edition Software version 25.3. The invalid assignments can safely be ignored. The compilation and simulation results are valid. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is there no response in AXI read data channel in Intel® Stratix® 10 MX FPGA High Bandwidth Memory (HBM2) IP simulation?
Description When the signals in HBM2 AXI interface are set to unknown status before and after the read command in HBM2 simulation, you might see that there is no response in HBM2 AXI read data channel. Resolution Because there is no unkown status in actual hardware behavior, the signals in AXI interface will be captured as either 0 or 1, so the unknown status in simulation are not expected. To work around this, you can set the signlas in HBM2 AXI interface in simulation to random values instead of setting them to unknown status.Why are XTS data packets corrupted during interleaving of GCM and XTS profiles when using the Symmetric Cryptographic Intel® FPGA Hard IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and later, XTS data packets can be corrupted when keys and data are interleaved independently across channels during interleaving of GCM and XTS profiles when using the Symmetric Cryptographic Intel® FPGA Hard IP. Resolution Workaround for 1x512-bit mode: Program data with keys before interleaving and send a minimum of one data cycle with every key programming cycle. Resolution for 2x256-bit mode: Support for 2x 256-bit mode has been removed from the Intel® Quartus® Prime Pro Edition Software version 22.1 and later.Why do I see Support-Logic Generation error when implementing the F-Tile Ethernet Intel® FPGA Hard IP with '50GE-2', 'MII PCS only' and 'None" FEC mode options selected ?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, you may see a Support-Logic Generation error when implementing F-Tile Ethernet Intel FPGA Hard IP with '50GE-2', 'MII PCS only' and 'None" FEC mode options selected. The Intel® Quartus® Prime Pro Edition Software versions 21.4 and earlier are not affected. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.2.Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the error below will be seen when using Questasim* Intel® FPGA Edition to simulate a design that instantiates the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*. Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined Resolution To work around this problem, use the Siemens* Questa* Advanced Simulator full version. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition Software.