Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s))
Description You may see the errors below in the Quartus® Prime Pro Edition Software version 20.3 when compiling the Agilex™ 3 FPGA PHYLite IP. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 pin, which is within ed_synth ed_synth. Error(16234): No legal location could be found out of 1772 considered location(s). Reasons why each location could not be used are summarized below: Error(175005): Could not find a location with: DQS_x36 (1 location affected) Error(175008): Location was not in the legal region (1771 locations affected) Resolution These errors are due to hardware limitations. A configuration of the Agilex™ 3 FPGA PHYLite IP, where X8/X9 and X32/X36 DQS groups are used simultaneously in the same IO48 sub-bank, is unsupported.Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1
Description You may encounter the below fitter error when designing with the Agilex™ 5 FPGA MIPI D-PHY IP in Quartus® Prime Pro Edition version 24.1 when using a specific reference clock frequency and bit rate combination. Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid, and the Fitter must be restarted. Resolution These errors are caused by an invalid combination of reference clock frequency and operating bit rate. These combinations will be removed in a future release of the Quartus® Prime Pro Edition Software.
Why are there PCIe* functional failures observed after a Configuration via Protocol (CvP) update in Agilex® 7 FPGA devices (R-Tile) CvP designs?
Description Due to a problem in Quartus® Prime Pro Edition software versions 25.3.1 and earlier, when using Configuration via Protocol (CvP) for Agilex® 7 FPGA devices (R-Tile), you may observe PCIe* functional failures after performing a CvP update, as the PCIe interface becomes non-functional. During the CvP update, the FPGA fabric is reconfigured and held in reset, while the PCIe Hard IP is not reset. This issue occurs because the R-Tile RTL is unable to handle the handshaking between the PCIe Hard IP and the fabric after the CvP update. Note that this issue does not cause the PCIe link to go down. This issue affects designs using R-Tile with both CvP and PCIe. Designs using R-Tile without CvP are not affected. This issue occurs in the following flow: CvP Periphery image CvP Initialization CvP Update PCIe activity Issue observed The following sequences will not trigger the problem: A CvP update without PCIe activity after CvP Initialization PCIe activity without a CvP Update after CvP Initialization Resolution To work around this problem, reconfigure the FPGA. Note that this fix may introduce a few seconds of additional delay during the CvP update in the teardown process. This delay occurs after the core.rbf file is transferred during every CvP update. During teardown, the CvP driver polls the CVP_CONFIG_READY bit in the CvP Status Register until CVP_CONFIG_READY equals 0, which accounts for the additional delay. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1. Related IP R-Tile Avalon Streaming IP for PCI Express Multi Channel DMA IP for PCI Express AXI Streaming IP for PCI ExpressWhy does reconfiguration of Intel® Stratix® 10 MX devices fail when the hbm_only_reset_in port of High Bandwidth Memory (HBM2) Interface Intel® FPGA IP is connected to the output of Intel® FPGA Reset Release FPGA IP or other core logic?
Description When using Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, performing reconfiguration of Intel® Stratix® 10 MX devices in user mode will fail if the hbm_only_reset_in port for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP is connected to the output of Intel® FPGA Reset Release FPGA IP or other core logic. During reconfiguration, if the hbm_only_reset_in is driven with logic value 1'b1, then the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP will always be in a reset state and result in configuration failure. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2. To resolve this problem, update the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software 21.2/21.3/21.4/22.1/22.2/22.3. The latest device manager firmware versions are available from the following link: What is the latest device firmware for Intel® Agilex™ and Intel® Stratix® 10 devices?When using the Intel Agilex® 7 FPGA P-Tile, why are simulation errors seen when compiling the Multi-Channel DMA Intel® FPGA IP for PCI Express testbench in the Cadence Xcelium simulator?
Description As stated in Table 34. Supported Simulators for MCDMA IP P-Tile of the Multi-Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide, the Cadence Xcelium simulator is not supported if the simulation of this IP configuration is attempted using Cadence Xcelium, the following error will be seen: $>./xcelium_setup.sh ~~~~~ xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics. xmelab: *F,CUMSTS: Timescale directive missing on one or more modules. xmsim: 20.03-s005: (c) Copyright 1995-2020 Cadence Design Systems, Inc. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_tb.pcie_ed_tb' does not exist in the libraries. Resolution Support for the Cadence Xcelium simulator of this IP configuration is planned for a future release of the Intel® Quartus® Prime Pro Edition Software. To work around this problem with the existing IP release, please ensure a supported simulator is used.Why does accessing an invalid register address on the AXI-Lite management bus of the MACsec Intel® FPGA IP cause the bus to hang?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, access to an invalid address on the AXI-Lite management bus of the MACsec Intel® FPGA IP will cause the bus to hang. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software v22.2, do not attempt to access invalid (unspecified) register addresses on the AXI-Lite bus. This problem has been fixed starting with the release of version 22.3 of the Intel® Quartus® Prime Pro Edition software.Why are UnsupReq, NonFatalErr, and CorrErr statuses asserted after power cycle or OS reboot while using the P-Tile Intel® FPGA IP for PCI Express?
Description You may find UnsupReq, NonFatalErr, and CorrErr status asserted after power cycle or operating system (OS) reboot when using the P-Tile Intel® FPGA IP for PCI Express. Resolution According to the PCI Express Base specification revision 4.0 version 1.0, during the enumeration of a non-existent device or function, completion with UR status is sent, and UnsupReq is asserted. Meanwhile, Non-Fatal Advisory Error is determined, and CorrErr and NonFatalErr are asserted. To work around this problem, clear the UnsupReq, NonFatalErr, and CorrErr statuses in the PCI Express configuration space registers before checking them during data transactions. This problem is not planned to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.