Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s))
Description You may see the errors below in the Quartus® Prime Pro Edition Software version 20.3 when compiling the Agilex™ 3 FPGA PHYLite IP. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 pin, which is within ed_synth ed_synth. Error(16234): No legal location could be found out of 1772 considered location(s). Reasons why each location could not be used are summarized below: Error(175005): Could not find a location with: DQS_x36 (1 location affected) Error(175008): Location was not in the legal region (1771 locations affected) Resolution These errors are due to hardware limitations. A configuration of the Agilex™ 3 FPGA PHYLite IP, where X8/X9 and X32/X36 DQS groups are used simultaneously in the same IO48 sub-bank, is unsupported.Why does the GTS JESD204B/C FPGA IP and Design Example generation fail on Agilex™ 3 FPGA and Agilex™ 5 FPGA devices when selecting System or HVIO PLL clocking mode?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter an error message like the following when generating the GTS JESD204B/C FPGA IP Design Example. "Error: phy_inst.inst_directphy: System/HVIO PLL frequency "307.2" cannot be smaller than transceiver's parallel clock frequency "858.0" The following IP configuration steps may lead to the above error: Set the Data rate to a specific value Set the Datapath clocking mode System PLL Enable the example design generation Enable Simulation and/or Synthesis in the Example Design Files section Increase the data rate to a value higher than the data rate set in step 1 Generate the IP or Example Design *Note that this problem will not occur when you use a data rate set in Step 5 lower than the data rate set in Step 1. Resolution When you encounter this error, use the following workaround: Disable example design generation Update the System PLL frequency for the latest data rate Enable example design generation Generate the IP or Example Design This problem will be fixed in a future release of the Quartus Prime Pro Edition Software.Why does the simulation of the MIPI DSI-2 FPGA IP Design Example fail with default timing parameter settings?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, users may observe the following error when simulating the MIPI DSI-2 FPGA IP Design Example using the default video timing parameter settings. Fatal: dsi2_ed_sim_tb.dut.dsi2_tx.dsi2_tx.dsi2.mipi_dsi2_tx_inst.<protected>.<protected>: Error: axis_m does not accept back pressure Resolution To work around this problem in the Quartus Prime Pro Edition software version 25.1.1, update the video paramaters as below : Dimension: Default value for HTOTAL: 2176 Default value for VTOTAL: 100 Blank Timing: Default value for HB_END: 2048 Default value for V1B_START: 0 Default value for V1B_END: 4 Syn Timing Default value for HS_START: 52 Default value for HS_END: 100 Default value for V1S_VSTART: 2 Default value for V1S_HSTART: 52 Default value for V1S_VEND: 3 Default value for V1S_HEND: 52 This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.
Why o_rx_pcs_fully_aligned does not assert for 40GE-4 Advanced mode F-Tile Ethernet Hard IP design when Custom Ethernet line rate > 63Gbps?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, you might observe o_rx_pcs_fully_aligned does not assert for the F-Tile Ethernet Hard IP design with below configurations: Advanced mode: Enabled Ethernet mode: 40GE-4 Custom Ethernet line rate: > 63 Gbps Resolution There is no workaround. There is no fix planned in the future. When advanced mode enabled for 40GE-4 design, supported custom Ethernet line rate is: 41.25~63 Gbps.Why does accessing an invalid register address on the AXI-Lite management bus of the MACsec Intel® FPGA IP cause the bus to hang?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, access to an invalid address on the AXI-Lite management bus of the MACsec Intel® FPGA IP will cause the bus to hang. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software v22.2, do not attempt to access invalid (unspecified) register addresses on the AXI-Lite bus. This problem has been fixed starting with the release of version 22.3 of the Intel® Quartus® Prime Pro Edition software.Why do I see elaboration errors on the Cadence Xcelium* simulator when using the Agilex™ 7 F-Tile IPs?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, Agilex™ 7 F-Tile IPs may show elaboration time errors when using the Cadence Xcelium* simulator similar to the error shown below: xmelab: *E,CUVIMG (<QUARTUS_INSTALL_DIR>/ libraries/megafunctions/ftileb_ag_v0.sv,624316): Implicit name not allowed in hierarchical name. Resolution To workaround this problem, use the following Cadence Xcelium* simulator-specific option: xmelab: *E,CUVIMG (<QUARTUS_INSTALL_DIR>/libraries/megafunctions/ftileb_ag_v0.sv,624316): Implicit name not allowed in hierarchical name. Use elaboration switch (-genhier) in the simulation compilation script. Example: xmelab -genhier -relax -timescale '1 ps / 1 fs' -genhier -access +rwc <top_level_name> This problem has been fixed in version 24.1 of the Quartus® Prime Pro Edition Software.Why does the GTS SDI II IP Multi-rate Serial Loopback Design Example fail to achieve lock on Agilex™ 5 FPGA E-Series Modular Development Kit at 12G data rate?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may observe the rx_align, rx_frame and rx_trs signals fail to achieve lock when running the GTS SDI II IP Multi-rate Serial Loopback Design Example on Agilex™ 5 FPGA E-Series Modular Development Kit at 12G data rate. Resolution There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the Design Closure Summary fail in the Agilex™ 5 FPGA and Agilex™ 7 FPGA HDMI IP Example Designs?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may observe the Design Assistant Summary flagged with High Severity Violations and Design Closure Summary marked as Fail in the Agilex™ 5 FPGA and Agilex™ 7 FPGA HDMI IP Example Designs. These warnings can be safely ignored. Resolution There is no workaround. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.