Why doesn’t the output frequency of the System PLL match the setting in the GTS System PLL Clocks IP?
Description Due to a device problem, some reference clock frequency options in the dropdown list in the IP are no longer valid for certain output frequencies. Selecting the invalid reference clock options will result in incorrect System PLL output frequencies. However, the System PLL lock status signal remains asserted. Resolution Download the TCL script (find_mcnt.tcl) to determine whether the reference clock frequency selected in the GTS System PLL Clocks IP is valid. If the reference clock frequency is not valid, the script recommends the following workarounds: List of alternate reference clock frequencies while keeping the same output frequency. Two alternate higher System PLL output frequencies while keeping the same reference clock frequency. You need to run the transceiver channels driven by the impacted System PLLs in custom cadence mode. In certain cases, the script will suggest that the same output & input clock frequencies can be retained. This option is possible only if you install the patch for the Quartus® Prime Pro Edition Software version 25.3 or migrate to future Quartus Prime Pro Edition Software versions. Copy the TCL script (find_mcnt.tcl) to each of the generated IP folders of the GTS System PLL Clocks IP in your Quartus Prime Pro Edition Software project. For the Linux* operating system, change directory to the IP folder and execute the command "tclsh find_mcnt.tcl". For Windows* operating system, run the script from the Tcl Console within the Quartus Prime Pro Edition Software GUI. A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3. Download and install Patch 0.15 from the files below. Recommended actions: Customer Design Status Recommended Actions Design not impacted If the design is final and there is no plan to change the System PLL output frequency or reference clock frequency in future revisions, no further action is needed. If you change the design in the future, either migrate your design to Quartus Prime Pro Edition Software versions 25.3.1 or later, or install the patch for Quartus Prime Pro Edition Software version 25.3. Design impacted Implement one of the workarounds suggested. In addition, migrate your design to the Quartus Prime Pro Edition Software version 25.3.1 or later. If you need to keep your design in the Quartus Prime Pro Edition Software version 25.3, install the patch, re-generate the GTS System PLL Clocks IP, and recompile your Quartus project. The invalid reference clock frequency options will be removed in a future Quartus Prime Pro Edition Software version.Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s))
Description You may see the errors below in the Quartus® Prime Pro Edition Software version 20.3 when compiling the Agilex™ 3 FPGA PHYLite IP. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 pin, which is within ed_synth ed_synth. Error(16234): No legal location could be found out of 1772 considered location(s). Reasons why each location could not be used are summarized below: Error(175005): Could not find a location with: DQS_x36 (1 location affected) Error(175008): Location was not in the legal region (1771 locations affected) Resolution These errors are due to hardware limitations. A configuration of the Agilex™ 3 FPGA PHYLite IP, where X8/X9 and X32/X36 DQS groups are used simultaneously in the same IO48 sub-bank, is unsupported.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.
Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" Resolution Workaround: To work around this problem, follow the steps below: Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” Save the updated .ip file. Reopen the modified .ip file in the Quartus® IP Parameter Editor. Depending on your use case, click “Generate Example Design” or “Generate HDL.”Why does the simulation of the MIPI DSI-2 FPGA IP Design Example fail with default timing parameter settings?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, users may observe the following error when simulating the MIPI DSI-2 FPGA IP Design Example using the default video timing parameter settings. Fatal: dsi2_ed_sim_tb.dut.dsi2_tx.dsi2_tx.dsi2.mipi_dsi2_tx_inst.<protected>.<protected>: Error: axis_m does not accept back pressure Resolution To work around this problem in the Quartus Prime Pro Edition software version 25.1.1, update the video paramaters as below : Dimension: Default value for HTOTAL: 2176 Default value for VTOTAL: 100 Blank Timing: Default value for HB_END: 2048 Default value for V1B_START: 0 Default value for V1B_END: 4 Syn Timing Default value for HS_START: 52 Default value for HS_END: 100 Default value for V1S_VSTART: 2 Default value for V1S_HSTART: 52 Default value for V1S_VEND: 3 Default value for V1S_HEND: 52 This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1
Description You may encounter the below fitter error when designing with the Agilex™ 5 FPGA MIPI D-PHY IP in Quartus® Prime Pro Edition version 24.1 when using a specific reference clock frequency and bit rate combination. Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid, and the Fitter must be restarted. Resolution These errors are caused by an invalid combination of reference clock frequency and operating bit rate. These combinations will be removed in a future release of the Quartus® Prime Pro Edition Software.Why does the Intel Agilex® 7 F-Tile SDI II FPGA IP design example fail to compile at the Support-Logic Generation stage?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.4, the Intel Agilex® 7 F-Tile SDI II FPGA IP design example will fail at the Support-Logic Generation stage during compilation with the following error message: Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.4. Download and install Patch 0.01 from the following links: Version 21.4 Patch 0.01 for Windows (.exe) Version 21.4 Patch 0.01 for Linux (.run) Readme for version 21.4 Patch 0.01 (.txt) This problem is being fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.1.Is there a known issue with the Flash Chip Select setting in the Generic Serial Flash Interface Intel® FPGA IP when Advanced Mode is enabled?
Description Yes, due to a problem in Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, when Advanced Mode is enabled in the Generic Serial Flash Interface Intel® FPGA IP, the Flash Chip Select setting is not being mapped correctly to the Control Register bits [7:4] For example, when the Flash Chip Select is set to '1', rather than the Control Register bits [7:4] being set to '000', a bit setting of '001' is applied. Resolution To avoid this issue, disable Advanced Mode. This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 23.1.Why do I get a fitter compilation error (Error 169285) when I use the Generic Serial Flash Interface IP in my design?
Description When compiling a design with the Generic Serial Flash Interface IP, the following error may occur: Error(169285): Too many input or bidirectional pins (17) are assigned in I/O bank 3A. This error does not appear if the Generic Serial Flash Interface IP is removed. The pin-out file shows exactly 16 user I/Os for Bank 3A, but the error reports 17 pins. The issue is triggered when using the following Quartus.ini assignment: fiomgr_enable_spi_timing=on With this setting enabled, the Fitter counts both 16 user I/Os and 10 dedicated configuration pins in Bank 3A. Because the Fitter rule allows a maximum of 16 user I/Os, the additional visibility of the 10 configuration pins causes the rule check to fail, resulting in the error. Resolution This problem is fixed starting with Quartus® Prime Standard Edition Software version 24.1. For earlier versions, a patch is available: Quartus® Prime Standard Edition v20.1.1 → Patch 1.12std If you require this patch, please contact Premier Support to request access.