Why do I get an error in Platform Designer during the Generate HDL process for systems which include the DDR3 SDRAM Controller with UniPHY IP core
Description Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core. Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Resolution To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does the F-Tile JESD204C Altera® IP Design Example fail to compile when migrated from a previous version of the Quartus® Prime Pro Edition Software to version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile JESD204C Altera® IP Design Example will fail to compile when migrated from any previous version of the Quartus® Prime Pro Edition Software to version 24.3. Resolution Follow the instructions below to work around this problem in the Quartus® Prime Pro Edition Software version 24.3 by manually editing the module to remove the unused port. In the Files tab under Project Navigator window, locate the ed_control IP file (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control.ip) . Expand the directory and find the target module (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control/synth/j204c_f_<data path>_ss_ed_control.v) Comment out the all “csr_tst_ctl_tst_control_error_inject” ports. For example: // output wire csr_tst_ctl_tst_control_error_inject The problem has been fixed starting with Quartus® Prime Pro Edition software version 24.3.1.
Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" Resolution Workaround: To work around this problem, follow the steps below: Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” Save the updated .ip file. Reopen the modified .ip file in the Quartus® IP Parameter Editor. Depending on your use case, click “Generate Example Design” or “Generate HDL.”Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s))
Description You may see the errors below in the Quartus® Prime Pro Edition Software version 20.3 when compiling the Agilex™ 3 FPGA PHYLite IP. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 pin, which is within ed_synth ed_synth. Error(16234): No legal location could be found out of 1772 considered location(s). Reasons why each location could not be used are summarized below: Error(175005): Could not find a location with: DQS_x36 (1 location affected) Error(175008): Location was not in the legal region (1771 locations affected) Resolution These errors are due to hardware limitations. A configuration of the Agilex™ 3 FPGA PHYLite IP, where X8/X9 and X32/X36 DQS groups are used simultaneously in the same IO48 sub-bank, is unsupported.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1
Description You may encounter the below fitter error when designing with the Agilex™ 5 FPGA MIPI D-PHY IP in Quartus® Prime Pro Edition version 24.1 when using a specific reference clock frequency and bit rate combination. Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_1 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid, and the Fitter must be restarted. Resolution These errors are caused by an invalid combination of reference clock frequency and operating bit rate. These combinations will be removed in a future release of the Quartus® Prime Pro Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex® 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows* and Linux* below This patch ensures the transmitter maintains negative running disparity for Agilex® 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1.Why does the Intel® Quartus® Prime Software device pin-out show a different number of pins compared to the Intel® Cyclone® 10 LP Device Overview document?
Description When targeting Intel® Cyclone® 10 LP devices in the Intel® Quartus® Prime Software, you will notice that there is 1 pin difference in the total pin count if compared to the Intel® Cyclone® 10 LP Maximum Resources in the Intel® Cyclone® 10 LP Device Overview document. For example, the Intel® Quartus® Prime Software lists 151 I/O pins for 10CL025YU256I7G, but in other documents it is listed as 150 I/O pins. Resolution This difference is because in the Intel® Quartus® Prime Software, the DCLK is counted as an I/O, since it can be used in user mode but in the respective device pin table, DCLK is not counted as an I/O. Thus, you will find 1 pin difference between what is stated in the Intel Cyclone 10 LP Device Overview document and the Intel Quartus Prime Software.Why does compilation fail during the Logic Generation Stage with the F-Tile SDI II Intel® FPGA IP in TX and RX simplex mode and when placed in the same channel with the Intel Agilex® 7 device?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the F-Tile SDI II Intel® FPGA IP will fail during compilation process when merging both TX and RX simplex mode in the same channel, the following error messages will appear during the Logic Generation stage: Error (21842): Support logic cannot be generated because IP components used in the design have conflicting settings Error: Design cannot be programmed onto available F-Tiles because given location constraints are conflicting, or because the design requires more resources compared to what is available on current device Error: Quartus Prime Logic Generation Tool was unsuccessful. 22 errors, 0 warnings Error (21794): Quartus Prime Full Compilation was unsuccessful. 24 errors, 2 warnings This problem is due to the Intel® Quartus® Prime Pro Edition Software being unable to merge the single SDI II TX profile with multiple profiles of the SDI II RX when in multirate mode. Resolution To work around this problem when using TX and RX in simplex mode, the TX and RX lanes must be seperated into two different channels to pass compilation at the Logic Generation stage. This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software 22.2 version.Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 BYTE_CONTROL(s)). Fix the errors described in the submessages, and then rerun the Fitter.
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you may encounter the below fitter error when entering an odd number (1 or 3 or 5 or 7) in the 'Byte Locations' setting in the MIPI D-PHY IP GUI when designing with the Agilex® 3 FPGA or Agilex® 5 FPGA MIPI D-PHY IP. Error(175001): The Fitter cannot place 1 BYTE_CONTROL, which is within Generic Component dphy_dut_dphy. Info(14596): Information about the failing component(s): Info(175028): The BYTE_CONTROL name(s): dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|dphy_link[0].dphy_link_used.io_blk_inst|byte_in_link[0].byte_control_wrap_inst|byte_control_inst Error(16234): No legal location could be found out of 32 considered location(s). Reasons why each location could not be used are summarized below: Error(175006): There is no routing connectivity between the BYTE_CONTROL and the BYTE_CONTROL Error(175022): The BYTE_CONTROL could not be placed in any location to satisfy its connectivity requirements Info(175029): 16 locations affected Error(175006): There is no routing connectivity between the BYTE_CONTROL and destination BYTE Info(175027): Destination: BYTE dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|dphy_link[0].dphy_link_used.io_blk_inst|byte_in_link[0].byte_wrap_inst|byte_inst Error(175022): The BYTE_CONTROL could not be placed in any location to satisfy its connectivity requirements Info(175021): The destination BYTE was placed in location BYTE_X126_Y147_N106 Info(175029): 16 locations affected Resolution To work around this problem, generate the MIPI D-PHY Design Example with only even number (0 or 2 or 4 or 6) in the 'Byte Locations' setting in the MIPI D-PHY IP GUI. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Why does the SDI II Intel® FPGA IP Multi-rate (up to 12G-SDI) design fail to work when merging both TX and RX simplex mode in the same channel with the Intel Agilex® 7 device?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 with patch 0.06 installed, the F-tile SDI II Intel® FPGA IP Multi-rate (up to 12G-SDI) design will fail to work when merging both TX and RX simplex mode in the same channel. This issue does not impact the HD-SDI, 3G-SDI, and Triple rate (up to 3G-SDI) designs with both TX and RX simplex mode in the same channel. Resolution To work around this problem, the TX and RX lanes must be separated into two different channels when using TX and RX simplex mode in Multi rate designs. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.