Why do I get a fitter compilation error (Error 169285) when I use the Generic Serial Flash Interface IP in my design?

Description

When compiling a design with the Generic Serial Flash Interface IP, the following error may occur:

Error(169285): Too many input or bidirectional pins (17) are assigned in I/O bank 3A.

• This error does not appear if the Generic Serial Flash Interface IP is removed.

• The pin-out file shows exactly 16 user I/Os for Bank 3A, but the error reports 17 pins.

• The issue is triggered when using the following Quartus.ini assignment:

fiomgr_enable_spi_timing=on

With this setting enabled, the Fitter counts both 16 user I/Os and 10 dedicated configuration pins in Bank 3A. Because the Fitter rule allows a maximum of 16 user I/Os, the additional visibility of the 10 configuration pins causes the rule check to fail, resulting in the error.

Resolution

This problem is fixed starting with Quartus® Prime Standard Edition Software version 24.1.

For earlier versions, a patch is available:

• Quartus® Prime Standard Edition v20.1.1 → Patch 1.12std

If you require this patch, please contact Premier Support to request access.