Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does the R-tile AXI Multichannel DMA IP for PCI Express* Example Design (AXI-S Packet Generate/Check variant) generation fail with Enable User MSI-X IP is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3, 25.3.1 and 26.1, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User MSI-X option is selected under the PCIe Settings --> MCDMA Settings tab The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: add_connection GEN_CHK_M0.usr_msix DUT.user_msix: Cannot connect GEN_CHK_M0.usr_msix to DUT.user_msix. Error: Failed to generate example design example_design to: <path> This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User MSI-X option is selected. Resolution To work around this problem, do not select the Enable User MSI-X option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* Example Design. There is no other workaround for Quartus Prime Pro Edition Software versions 25.3, 25.3.1, and 26.1. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example (Packet Generate/Check variant) fail when using Siemens Questa* simulator in Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1, simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example with the Packet Generate/Check variant may fail when using the Siemens Questa* simulator. The failure is observed after the DMA queue reset sequence finishes, and a PIO register write is issued. Simulation then stalls with no further activity and terminates with an inactivity timeout after some time. An example of the messages observed in the simulation log is shown below: INFO: 43000 ns H2D: Got Status for Channel 0 INFO: 43000 ns D2H: Performing Channel 0 Queue Reset INFO: 47000 ns D2H: Channel 0 Queue Reset...done INFO: 47000 ns PIO_WRITE_REG 8000000100001000 FATAL: 4000000 ns Simulation stopped due to inactivity! FAILURE: Simulation stopped due to Fatal error! FAILURE: Simulation stopped due to error! ** Note: $stop : ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v(146) Time: 4 ms Iteration: 3 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/g_bfm/u1/rp/inst/apps/genblk1/drvr Break at ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v line 146 This issue affects simulation only and does not impact hardware functionality. Resolution To work around this problem, generate the F-Tile Multi Channel DMA FPGA IP for PCI Express Design Example (Packet Generate/Check variant) and run simulation using Quartus® Prime Pro Edition Software version 25.1.1. The problem is not observed in that release. There is no other workaround for Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design generation fail with Enable User FLR is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3 and later, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User FLR option is selected under the PCIe Settings --> MCDMA Settings tab. The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: pcie_axi_mcdma_0: Fail .qsys synthesis generation Error: pcie_axi_mcdma_0: Unable to generated HDL Files for the system .qsys Error: Failed to generate example design example_design to: <path> Generate Example Design: completed with errors. This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User FLR option is selected. Resolution To work around this problem, do not select the Enable User FLR option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design. There is currently no other workaround for Quartus® Prime Pro Edition Software versions 25.3 and later. This problem is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.
Why does the PHY Lite for Parallel Interfaces IP without dynamic reconfiguration in the Agilex® 7 FPGA M-Series fail to assert interface_locked in the Quartus® Prime Pro Edition Software version 23.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the PHY Lite for Parallel Interfaces IP without dynamic reconfiguration will fail to assert the interface_locked signal in the Agilex® 7 FPGA M-Series. Resolution To work around this problem, turn on dynamic reconfiguration mode in the IP Parameter Editor Pro GUI and instantiate the Calibration IP in your RTL design when using the PHY Lite for Parallel Interfaces IP in the Agilex® 7 FPGA M-Series, even if the design does not require dynamic calibration. Please refer to an example design with dynamic reconfiguration to connect the Calibration IP to the PHY Lite for Parallel Interfaces IP. The problem has been fixed starting with Quartus® Prime Pro Edition software version 24.1.Why does system hang when device operates with R-Tile Multi Channel DMA IP for PCI Express* ?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, you might observe that the host reports a completion timeout error and system hangs when running DMA. Resolution To work around this problem, directly disable MCTP option in BIOS and reboot the system.Why do I see the wrong IP parameter in Agilex® 5 FPGA E-Series GTS HDMI IP file after generation from GUI?
Description You may see wrong ipxact parameter (PIXELS_PER_CLOCK/HDMI21_VARIANT) in IP file Resolution Workaround is to open the IP file by text editor and change the ipxact parameter (PIXELS_PER_CLOCK/HDMI21_VARIANT) as attached file and generate the IP again.Why do I see generation error message when generating F-Tile Multi Channel DMA IP for PCI Express* Example Design using Quartus® Prime Pro Edition software version 24.1 for Windows*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and onwards for Windows, you may see the below error message when generating F-Tile Multi Channel DMA IP for PCI Express* Example Design. "file delete -force -- "${ORI_TEMP_PATH}/pcie_ed_rp/pcie.qsf"" (procedure "::intel_pcie_ftile_mcdma::generate_design_example_files" line 230) invoked from within "::intel_pcie_ftile_mcdma::generate_design_example_files ${QSYSTemPath} ${QSYSTemName} $TEMPPATH" (procedure "::intel_pcie_ftile_mcdma::generate_dynamic_qsys" line 1819) invoked from within "::intel_pcie_ftile_mcdma::generate_dynamic_qsys" (procedure "::intel_pcie_ftile_mcdma::dynamic_example_design" line 10) invoked from within "::intel_pcie_ftile_mcdma::dynamic_example_design" (procedure "::intel_pcie_ftile_mcdma::fileset::callback_example_design" line 2) invoked from within "::intel_pcie_ftile_mcdma::fileset::callback_example_design intel_pcie_ftile_mcdma_0_example_design" Error: Failed to generate example design example_design to: C:\altera_pro\24.1\quartus\bin64\intel_pcie_ftile_mcdma_0_example_design Resolution To resolve this problem, use one of the following methods: Perform the design example generation step in a Linux* environment. Use Quartus Prime Pro Edition software version 25.3. During the design example generation, disable the “Simulation” option in the IP GUI. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why does the simulation of the MIPI DSI-2 FPGA IP Design Example fail when the vertical timing (Vtotal) parameter is modified?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and 25.3, simulation of the MIPI DSI-2 FPGA IP Design Example will fail if vertical timing parameters (VTOTAL) are modified. This problem occurs because the simulation environment is fixed for a 96-line vertical active region (VTOTAL – VB_END), which causes mismatches with other configurations. Horizontal timing changes work as long as the parameters remain consistent. This problem affects simulation only; the synthesized IP accepts any valid vertical timing configuration. Additionally: V1B_START must remain at line 0. Changing this parameter results in incorrect output. When modifying vertical timing, ensure: The active region ends at VTOTAL – 1. Adjust V1B and V1S based on blanking starting at line 0. This issue affects both simulation and synthesis of the IP. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.
