Why does the Low Latency 40G Ethernet IP drop non-PTP packets when PTP residence-time update is enabled?
Description Due to a problem in the Quartus® Standard Edition software version 21.1, you may see the Low Latency 40G Ethernet IP may drop large non-PTP packets when the tx_etstamp_ins_ctrl_residence_time_update (PTP residence-time update) is asserted. This problem is typically observed with jumbo frames of approximately 3000 bytes or larger. The affected packets may be counted at the RX interface but may not appear at the TX output. PTP packets themselves may continue to transmit correctly. This problem is not observed when tx_etstamp_ins_ctrl_residence_time_update (PTP residence-time update) is kept deasserted. Resolution A patch (21.1std patch 0.16std) is available to fix this problem for the Quartus Standard Edition Software version 21.1. To request the patch, contact your local Altera support representative. This problem is resolved in the Quartus Prime Pro Edition Software 26.1. Altera recommends migrating to the latest Quartus Prime Pro Edition Software to address this problem.Why do I see this warning message after enabled Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you will observe below. “warning check failed! > warning: no path is found satisfying assignment" “set_max_skew -from get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|in_wr_ptr_gray -to get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|write_crosser|sync.u|din_s1 -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 - This assignment will be ignored.” It happens when user enables the Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example. This problem happens due to the undefined path of the dc_fifo.sdc. Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why am I seeing High Severity DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" after enabled Transceiver Toolkit in Dual-Simplex Parallel loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you may see a DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" in the compilation report for the GTS SDI II Dual-Simplex Parallel Loopback design example when the transceiver toolkit is enabled. Resolution This DA Warning can be ignored in 26.1.1, and this problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.What is the time taken by the GTS Ethernet Hard IP for Tx and Rx reset release to mission mode?
Description On hardware, the GTS Ethernet Hard IP transitions to mission mode after reset release within the following times, measured from reset de-assertion to the corresponding ready indicators: Transmit (Tx): approximately 4.55 ms, until tx_lane_stable is asserted Receive (Rx): approximately 11.2 ms, until rx_pcs_ready is asserted Resolution The observed delay is expected behavior for the GTS Ethernet Hard IP; no workaround is required. The design should use these ready indicators to determine mission-mode readiness rather than relying on a fixed delay. Simulation times are shorter because of simplified fast simulation models. Additional Information Hardware time differs from simulation due to fast sim models. In simulation, the GTS Ethernet Hard IP enters mission mode after reset release within these times, Transmit (Tx): approximately 1 ms, until tx_lane_stable is asserted Receive (Rx): approximately 1.016 ms, until rx_pcs_ready is assertedeCPRI example design generation fails because of an environment-variable dependency
Description Due to a problem in the Quartus ® Prime Pro Edition software version 26.1, you may see an error saying "Error: no such variable (read trace on “::env(ACDS_DEST_ROOT)”)” may occur when trying to generate example design in eCPRI IP, as shown in the screenshot below. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 26.1, add environment variable “ACDS_DEST_ROOT” as Quartus installation path, for example, “C:\altera_pro\26.1”. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why are Toolkit instances (ETK, TTK) not detected for Agilex® 7 F-Tile Ethernet Hard IP in System-console after device configuration?
Description In designs using multiple instances of the Agilex® 7 F-Tile Ethernet Hard IP with Toolkit support enabled (ETK and TTK), the Toolkit instances may sometimes not be detected in the System Console GUI after programming the FPGA with the design .sof file. This behavior is caused by a problem in the F-Tile Ethernet Hard IP configuration. Resolution A patch is available to fix this problem for the Quartus Prime Pro Edition software version 25.3.1 and 26.1. Download and apply attached patches (1.32, 0.35) for intended Quartus version, which restores Toolkit visibility in the System Console GUI for the F-Tile Ethernet Hard IP. This problem is fixed beginning with the Quartus Prime Pro Edition software version 26.1.1.Why Do I Receive the Critical Warning IPC-40026: System Clock Frequency Mismatch in a GTS SDI II Design with Dynamic Reconfiguration?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1.1, a critical warning may be displayed when using the GTS SDI II Design Example. This warning occurs because the SysPLL parameter is configured with the GTS PMA/FEC Direct PHY IP (TX/RX Simplex) settings instead of the GTS PMA/FEC Direct PHY IP (Dynamic Reconfiguration) settings. Resolution This warning can be safely ignored, as it does not affect the functionality or operation of the design. This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why does the F-Tile JESD204C FPGA IP Example Design fail to generate when the data rate above 23 Gbps with a target development kit selected, showing an error requiring VSR_MODE_HIGH_LOSS even though this option is unavailable in the IP GUI?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, the VSR_MODE_HIGH_LOSS option was removed. User is expected to use VSR_MODE_LOW_LOSS instead, which provides the same functionality previously available in both modes. However, this change is not correctly reflected in the F-Tile JESD204C IP GUI. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.3, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1.Why does the GTS JESD204B IP and GTS JESD204C IP with HVIO PLL clocking mode enabled failed the Quartus® Fitter compilation?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may observe the following error during Fitter compilation: "One or more blocks are configured incorrectly and will not have the desired functionality. --bcm instance name: hvio_1_1" This error occurs because Quartus® automatically assigns the hvio_refclk* port to an illegal location during placement. Resolution To work around this problem, you can manually assign the hvio_refclk* port to a HVIO bank. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the Quartus® Logic Generation Tool report the TX Equalizer settings as 'Ignored' when creating a Tx-only example design for F-Tile JESD204C IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 23.4, you may observe the Quartus Logic Generation Tool incorrectly reports the TX Equalizer settings as 'Ignored' when creating a TX-only example design for F-Tile JESD204C IP. Resolution To work around this problem, you can manually configure the analog parameter instances in the .qsf file. set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=<parameters value>” -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=< parameters value >" -to "tx_serial_data_n[*]" This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3.1.
