Why are there PCIe* functional failures observed after a Configuration via Protocol (CvP) update in Agilex® 7 FPGA devices (R-Tile) CvP designs?
Description Due to a problem in Quartus® Prime Pro Edition software versions 25.3.1 and earlier, when using Configuration via Protocol (CvP) for Agilex® 7 FPGA devices (R-Tile), you may observe PCIe* functional failures after performing a CvP update, as the PCIe interface becomes non-functional. During the CvP update, the FPGA fabric is reconfigured and held in reset, while the PCIe Hard IP is not reset. This issue occurs because the R-Tile RTL is unable to handle the handshaking between the PCIe Hard IP and the fabric after the CvP update. Note that this issue does not cause the PCIe link to go down. This issue affects designs using R-Tile with both CvP and PCIe. Designs using R-Tile without CvP are not affected. This issue occurs in the following flow: CvP Periphery image CvP Initialization CvP Update PCIe activity Issue observed The following sequences will not trigger the problem: A CvP update without PCIe activity after CvP Initialization PCIe activity without a CvP Update after CvP Initialization Resolution To work around this problem, reconfigure the FPGA. Note that this fix may introduce a few seconds of additional delay during the CvP update in the teardown process. This delay occurs after the core.rbf file is transferred during every CvP update. During teardown, the CvP driver polls the CVP_CONFIG_READY bit in the CvP Status Register until CVP_CONFIG_READY equals 0, which accounts for the additional delay. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1. Related IP R-Tile Avalon Streaming IP for PCI Express Multi Channel DMA IP for PCI Express AXI Streaming IP for PCI ExpressWhy does PTP accuracy error go beyond +/- 1.5ns during dynamic reconfiguration between GTS Ethernet Hard IP and Triple-Speed Ethernet IP in Quartus® Prime Pro Edition version 26.1 and earlier?
Description When using the GTS Dynamic Reconfiguration Controller IP flow in Quartus® Prime Pro Edition version 26.1 or earlier to perform dynamic reconfiguration between the GTS Ethernet Hard IP and the Triple-Speed Ethernet (TSE) IP, the PTP (Precision Time Protocol) accuracy error for the GTS Ethernet Hard IP may exceed ±1.5ns in this scenario. This PTP accuracy problem does not occur with the TSE IP in this case. Resolution No workaround is available so far. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the Fitter report that F-Tile FHT supplies must be powered, when my design does not use FHT transceivers in an Agilex® 7 FPGA F‑Tile device compiled in the Quartus® Prime Pro software version 25.3.1 and earlier?
Description Due to a bug in the Quartus® Prime Pro software version 25.3.1 and earlier, the Fitter incorrectly reports that the VCCEHT_FHT_GXF, VCCERT1_FHT_GXF, and VCCERT2_FHT_GXF supplies must be powered, even though your Agilex® 7 FPGA F-Tile device design does not use FHT transceivers. The Agilex 7 FPGA Device Family Pin Connection Guidelines documents for F-Series, I-Series, and M-Series devices states "Tie to GND if there is no FHT channel used" for the VCCEHT_FHT_GXF, VCCERT1_FHT_GXF, and VCCERT2_FHT_GXF supplies. It is safe to power down your supplies in accordance with the Agilex 7 FPGA Device Family Pin Connection Guidelines documents for F-Series, I-Series, and M-Series devices. Resolution This problem will be fixed in a future version of the Quartus Prime Pro software.Why do I see timing violations between the F-Tile Dynamic Reconfiguration Suite IP and the F-Tile Avalon-Streaming IP for PCI Express* when using Quartus® Prime Pro Edition version 25.3 and earlier on Agilex® 7 FPGA devices?
Description When using Quartus® Prime Pro Edition software version 25.3 and earlier on Agilex® 7 FPGA devices, you might see timing violations between the F-Tile Dynamic Reconfiguration Suite IP and the F-Tile Avalon-Streaming IP for PCI Express* if the F-Tile Avalon-Streaming IP for PCI Express is instantiated inside a VHDL generate statement. This leads to incorrect timing assignments, which may be ignored. Resolution To work around this problem, you can instantiate the F-Tile Avalon-Streaming IP for PCI Express outside of any VHDL generate construct. This problem may be fixed in a future version of the Quartus® Prime Pro Edition software.Why does the simulation of External Memory Interfaces (EMIF) IP hang indefinitely for Agilex® 5 FPGA ES devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, simulation of External Memory Interfaces (EMIF) IP might not proceed when using Agilex® 5 FPGA ES devices. Resolution To work around this problem, choose Agilex® 5 FPGA production devices for functional simulation. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the TX Throughput value shown in Ethernet Toolkit for the F‑Tile Ethernet FPGA Hard IP Design Example not match the expected data rate?
Description In F‑Tile Ethernet FPGA Hard IP Design Example generated using Quartus® Prime Pro Edition software versions 25.3.1 and earlier, you may notice that the TX Throughput reported by the Ethernet Toolkit appears lower than the expected line rate. This behavior is expected. The ROM‑based packet generator included in the design example has the following characteristics: It defaults to a 64‑byte packet size, and It inserts non‑zero inter‑packet gaps (IPG) These factors inherently reduce the measured throughput compared to the theoretical maximum line rate. Resolution To accurately validate the TX Throughput of the design, Altera recommends to use a standard Ethernet traffic tester capable of running in client loopback mode. This allows to measure the actual TX throughput without limitations imposed by the built‑in ROM packet generator. There is no plan to fix this problem.Why do I see generation error message when generating F-Tile Multi Channel DMA IP for PCI Express* Example Design using Quartus® Prime Pro Edition software version 24.1 for Windows*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and onwards for Windows, you may see the below error message when generating F-Tile Multi Channel DMA IP for PCI Express* Example Design. "file delete -force -- "${ORI_TEMP_PATH}/pcie_ed_rp/pcie.qsf"" (procedure "::intel_pcie_ftile_mcdma::generate_design_example_files" line 230) invoked from within "::intel_pcie_ftile_mcdma::generate_design_example_files ${QSYSTemPath} ${QSYSTemName} $TEMPPATH" (procedure "::intel_pcie_ftile_mcdma::generate_dynamic_qsys" line 1819) invoked from within "::intel_pcie_ftile_mcdma::generate_dynamic_qsys" (procedure "::intel_pcie_ftile_mcdma::dynamic_example_design" line 10) invoked from within "::intel_pcie_ftile_mcdma::dynamic_example_design" (procedure "::intel_pcie_ftile_mcdma::fileset::callback_example_design" line 2) invoked from within "::intel_pcie_ftile_mcdma::fileset::callback_example_design intel_pcie_ftile_mcdma_0_example_design" Error: Failed to generate example design example_design to: C:\altera_pro\24.1\quartus\bin64\intel_pcie_ftile_mcdma_0_example_design Resolution To resolve this problem, use one of the following methods: Perform the design example generation step in a Linux* environment. Use Quartus Prime Pro Edition software version 25.3. During the design example generation, disable the “Simulation” option in the IP GUI. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the Design Closure Summary fail in the Agilex® 7 FPGA HDMI IP Example Designs after changing the Layout Options under the IP GUI ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may observe the Design Closure Summary including Timing Closure marked as Fail in the Agilex® 7 FPGA F-Tile HDMI IP Design Example. Additionally, you may notice that the pll_frl_rx_outclk0 frequency is flagged as extremely high. This problem occurs when you change the “Layout Options” from its default values into any other value in the IP GUI. Resolution To work around this problem, follow the steps below: 1. go to "project" tab at Quartus -> Clean Project 2. locate directory rtl/ip/nios/nios_intel_hdmi_rx_phy/intel_hdmi_rx_phy_103/synth/nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v The filename nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v may vary for each generated design. Please verify files that start with nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103 (for example: nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxx.v). 3. Change the line #153 from [TMDS_1_GREEN_TRANSCEIVER_21] into [0] 4. Click saves and re-run the full compilation. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why is no video output displayed when migrating the F-Tile SDI II FPGA IP Design Example with 12G multi-rate from an older version to Quartus® Prime Pro Edition Software version 25.3.1 patch 1.10 ?
Description Due to an issue in the Quartus® Prime Pro Edition Software Programmer version 25.3.1, users may observe that no SDI II video output is displayed on the receiver side when using the F-tile SDI II FPGA IP Design Example with 12G multi-rate on Agilex® 7 FPGA devices. This issue is caused by forcing lock-to-data. For SDI dynamic reconfiguration designs, manual CDR lock mode with lock-to-ref enabled should be used. Resolution To solve this problem, use below method 1. Open Platform Designer of sdi_rx_sys.qsys 2. Disable fgt_rx_set_locktodata port, Enable fgt_rx_set_locktoref port 3. At System View Should not seeing fgt_rx_set_locktodata port Export fgt_rx_set_locktoref port out 4. Sync info and regenerate HDL 5. Open rx_top.sv file Comment out / remove fgt_rx_set_locktodata Add exported fgt_rx_set_locktoref port and connect to ~rx_set_ltd 6. Save and recompile design This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
Why does the High Bandwidth Memory (HBM2) Interface IP example design in the Intel® Stratix® 10 MX FPGA show min pulse width violation?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1 and earlier, you may see the min pulse width violation if you create an example design for the High Bandwidth Memory (HBM2) Interface IP targeting the Intel® Stratix® 10 MX FPGA. Resolution To work around this problem, download and install the Intel® Quartus® Prime Pro Edition Software version 19.1 patch 0.04 from the appropriate link below. After installing the patch, follow the steps shown in the Readme file. Download patch Quartus-19.1-0.04-windows.exe for Windows (.exe) Download patch Quartus-19.1-0.04-linux.run for Linux (.run) Download the Readme for patch Quartus-19.1-0.04-readme.txt (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.2.
