Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?

Description

Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP  created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. 

When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: 

Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" 

Resolution

Workaround:   

To work around this problem, follow the steps below: 

• Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” 

• Save the updated .ip file. 

• Reopen the modified .ip file in the Quartus® IP Parameter Editor. 

• Depending on your use case, click “Generate Example Design” or “Generate HDL.”