Why does the Low Latency 40G Ethernet IP drop non-PTP packets when PTP residence-time update is enabled?
Description Due to a problem in the Quartus® Standard Edition software version 21.1, you may see the Low Latency 40G Ethernet IP may drop large non-PTP packets when the tx_etstamp_ins_ctrl_residence_time_update (PTP residence-time update) is asserted. This problem is typically observed with jumbo frames of approximately 3000 bytes or larger. The affected packets may be counted at the RX interface but may not appear at the TX output. PTP packets themselves may continue to transmit correctly. This problem is not observed when tx_etstamp_ins_ctrl_residence_time_update (PTP residence-time update) is kept deasserted. Resolution A patch (21.1std patch 0.16std) is available to fix this problem for the Quartus Standard Edition Software version 21.1. To request the patch, contact your local Altera support representative. This problem is resolved in the Quartus Prime Pro Edition Software 26.1. Altera recommends migrating to the latest Quartus Prime Pro Edition Software to address this problem.eCPRI example design generation fails because of an environment-variable dependency
Description Due to a problem in the Quartus ® Prime Pro Edition software version 26.1, you may see an error saying "Error: no such variable (read trace on “::env(ACDS_DEST_ROOT)”)” may occur when trying to generate example design in eCPRI IP, as shown in the screenshot below. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 26.1, add environment variable “ACDS_DEST_ROOT” as Quartus installation path, for example, “C:\altera_pro\26.1”. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.What is the time taken by the GTS Ethernet Hard IP for Tx and Rx reset release to mission mode?
Description On hardware, the GTS Ethernet Hard IP transitions to mission mode after reset release within the following times, measured from reset de-assertion to the corresponding ready indicators: Transmit (Tx): approximately 4.55 ms, until tx_lane_stable is asserted Receive (Rx): approximately 11.2 ms, until rx_pcs_ready is asserted Resolution The observed delay is expected behavior for the GTS Ethernet Hard IP; no workaround is required. The design should use these ready indicators to determine mission-mode readiness rather than relying on a fixed delay. Simulation times are shorter because of simplified fast simulation models. Additional Information Hardware time differs from simulation due to fast sim models. In simulation, the GTS Ethernet Hard IP enters mission mode after reset release within these times, Transmit (Tx): approximately 1 ms, until tx_lane_stable is asserted Receive (Rx): approximately 1.016 ms, until rx_pcs_ready is assertedWhy Do I Receive the Critical Warning IPC-40026: System Clock Frequency Mismatch in a GTS SDI II Design with Dynamic Reconfiguration?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1.1, a critical warning may be displayed when using the GTS SDI II Design Example. This warning occurs because the SysPLL parameter is configured with the GTS PMA/FEC Direct PHY IP (TX/RX Simplex) settings instead of the GTS PMA/FEC Direct PHY IP (Dynamic Reconfiguration) settings. Resolution This warning can be safely ignored, as it does not affect the functionality or operation of the design. This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why do I see this warning message after enabled Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you will observe below. “warning check failed! > warning: no path is found satisfying assignment" “set_max_skew -from get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|in_wr_ptr_gray -to get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|write_crosser|sync.u|din_s1 -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 - This assignment will be ignored.” It happens when user enables the Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example. This problem happens due to the undefined path of the dc_fifo.sdc. Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why am I seeing High Severity DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" after enabled Transceiver Toolkit in Dual-Simplex Parallel loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you may see a DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" in the compilation report for the GTS SDI II Dual-Simplex Parallel Loopback design example when the transceiver toolkit is enabled. Resolution This DA Warning can be ignored in 26.1.1, and this problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why does the Quartus® fail Design Analysis when the 1G/2.5G/5G/10G Multirate Ethernet PHY IP and the F-Tile 1000BASE-KX Ethernet PHY IP are used in the same design?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1, Design Analysis might fail when a design targeting Agilex® F-Tile devices instantiates both of the following IP cores in the same project: 1G/2.5G/5G/10G Multirate Ethernet PHY IP (alt_mge_phy) F-Tile 1000BASE-KX Ethernet PHY IP (intel_mge_phy_f) Both IP cores include an RTL module named alt_mge_phy_pcs. The F-Tile 1000BASE-KX Ethernet PHY version of alt_mge_phy_pcs declares an additional parameter (ENABLE_GMII_ADAPTER) that is not present in the Multirate Ethernet PHY version. When Quartus elaborates the design, the Multirate Ethernet PHY definition of alt_mge_phy_pcs can be used for both instances, which causes a parameter mismatch and compilation failure for the F-Tile 1000BASE-KX Ethernet PHY IP. Using either IP alone does not trigger this failure. Resolution A patch (26.1 patch 0.28) is available to fix this problem for the Quartus Prime Pro Edition Software version 26.1. To request the patch, contact your local Altera support representative. This problem is scheduled to be resolved in a future release of the Quartus Prime Pro Edition Software.Why is the Ethernet MDIO IP unavailable in the IP Catalog and Platform Designer of Quartus® Prime Pro Edition Software version 26.1 for Agilex® 5 FPGA and Agilex® 3 FPGA designs?
Description From Quartus® Prime Pro Edition Software versions 24.1 through 26.1, the Ethernet MDIO IP is not available in the IP Catalog for Agilex® 5 FPGA and Agilex® 3 FPGA devices because support for these device families has not been enabled for the IP. Resolution A patch is available to resolve this issue in Quartus® Prime Pro Edition Software version 26.1. To install the fix: Download Patch 0.29 for your operating system. Install Patch 0.29 into your Quartus® Prime Pro Edition Software version 26.1 installation. The patch files are available below: Patch 0.29 for Windows (.exe) Patch 0.29 for Linux (.run) After installing the patch, the Ethernet MDIO IP will be available in the IP Catalog for Agilex® 5 FPGA and Agilex® 3 FPGA designs.Why does the F-Tile Low Latency 100G Ethernet IP not work when Ready Latency is set to 3?
Description Due to a problem in the Quartus Prime Pro Edition software version 26.1, you may see the F-Tile Low Latency 100G Ethernet IP doesn’t work when the IP for Ready Latency is set to 3 and it may result in incorrect TX client interface behavior because the Ready Latency parameter is not fully propagated through the generated IP hierarchy. There is no workaround in the current IP implementation because the Ready Latency GUI parameter is not used in the generated IP. Resolution A 26.1 patch (0.32) is available for this problem and it is attached to this article. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why am I seeing Synopsys VCSMX simulation failure using GTS SDI II Revision B Silicon Design Example ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, this problem is caused by incorrect atom parameter settings in the dynamic reconfiguration design example, resulting in Synopsys VCSMX simulation failures. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
