Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz.

Description

You may see the following error when entering 805.664062 MHz into the GTS System PLL Clocks IP "Output frequency C0" field, to match the frequency requirement in the GTS Ethernet Hard IP when configured for 25G-1 Ethernet on Agilex^TM 5 FPGA devices using the Quartus® Prime Pro software version 25.3.1 and earlier.

Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz.

Error: <filename>.intel_systemclk_gts_0: "Refclk frequency" (refclk_xcvr_freq_mhz_0) "156.250000" is out of range: "33.109482", "44.145976", "57.547433", "66.218964", "88.291952", "99.328446", "110.364940", "115.094866", "132.437928", "154.510916", "165.547410", "172.642299", "176.583904", "198.656892", "220.729880", "230.189732", "231.766374", "242.802868", "264.875856", "286.948844", "287.737165", "297.985338", "309.021832", "331.094820", "345.284598", "353.167808", "364.204302"

This problem is caused by the truncated display of the System PLL frequency in the GTS Ethernet Hard IP.

Resolution

To work around this problem you can enter 805.6640625 MHz into the “Output frequency C0" field of the GTS System PLL Clocks IP.

This problem may be fixed in a future version of the Quartus® Prime Pro software.