Why doesn’t the CDR lock signal assert in simulation for some F Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition in the Quartus® Prime Pro Edition software version 25.3.1?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see simulation failure that CDR lock signal doesn’t assert for some F‑Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition.

Resolution

There is no workaround currently.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro edition software.