Why isn’t a programming (SOF) file generated for the F-Tile Dynamic Reconfiguration Suite IP available for Example Designs when using the Quartus® Prime Pro Edition software versions 25.3 and earlier?
Description Due to starting from the Quartus® Prime Pro Edition software version 25.3 and earlier, it is compulsory to connect all the I/O ports to the correct PIN location. If any of the design I/O ports are floating and not properly connected, Quartus software will not be able to generate the programming file for the design compiled. This is mentioned in the Quartus Prime Pro Edition User Guide version 25.1.1 in 1.2. Generating Secondary Programming Files and provide the guidelines to the user on how to fix the Quartus software critical warning and successfully create the programming file for your design. Why don’t I get a programming file when I compile with the.... Similar programming (SOF) file generation problem you may observe when you generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting Target Development Kit with option 1) Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4xF-Tile) DK-SI-AGI027FA or 2) Agilex 7™ FPGA I-Series Transceiver-SoC Development Kit (Production 2 4xF-Tile) DK-SI-AGI027FC. As shown in the figure below. Resolution As a workaround, generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting the Target Development Kit with the option you want and compiling the design. Review the I/O Assignment Warnings report, found in the Place sub-section of the Fitter section of the compilation report. Alternatively, review the <revision>.fit.plan.rpt report file. For any pins in the I/O Assignment Warnings report that are reported as “Missing location assignment” or “Missing I/O standard,” add the appropriate location or I/O standard assignment. For help making these assignments, refer to Assigning I/O Pins. After adding any required assignments, recompile the design to generate a programming file. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the F-Tile Triple-Speed Ethernet IP Design Example fail during simulation on Windows using ModelSim* in the Quartus® Prime Pro Edition Software version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, the F-Tile Triple-Speed Ethernet (TSE) IP Design Example variant - “10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2xTBI PCS with F-Tile FGT Transceiver” - may fail during simulation on Windows platforms using ModelSim*. This problem occurs because the simulation script generated for the design example contains incorrect backslash (“\”) usage, which is not compatible with Windows* path formatting requirements. Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software version 24.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why isn’t rx_ready asserted for 1G lane after dynamically reconfigured from CPRI 10G to CPRI 1.2G when the firmware in the GTS Dynamic Reconfiguration Controller IP is disabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3.1, you may see rx_ready isn’t asserted at 1G CPRI when the firmware in the GTS Dynamic Reconfiguration Controller IP is disabled while Dynamic Reconfiguration(DR) process from CPRI 10G to CPRI 1.2G. This is because the firmware in the GTS Dynamic Reconfiguration Controller IP needs to be switched from Enable to Bypass mode. The software reset controller (SRC) logic was not correctly handling the state transition from Enable to Bypass mode. The state should be driven to ‘0’ when the firmware in the GTS Dynamic Reconfiguration Controller IP is disabled but this was not happening properly. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.1.1.Why does design compilation in the Quartus® Prime Pro Edition software version 25.3 and earlier fail during the fitter stage when the “Remove Redundant Logic Cells” option is enabled, and the F-Tile Dynamic Reconfiguration Suite IP is used in the design?
Description Many users enable the “Remove Redundant Logic Cells” option to optimize their designs for area and speed. However, when this Advanced Synthesis setting (REMOVE_REDUNDANT_LOGIC_CELLS) is turned on globally for F-Tile designs —particularly those that include the F-Tile Dynamic Reconfiguration Suite IP— it can inadvertently remove essential support logic (QTLG-generated logic) required for proper transceiver tile operation. As a result, design compilation in the Quartus® Prime Pro Edition software version 25.3 and earlier may fail during the fitter stage with errors related to transceiver logic placement, such as: Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts... Error (175001): The Fitter cannot place 1 HSSI_PLDADAPT_TX. The “Remove Redundant Logic Cells” option can be enabled in two ways: Through the Quartus Prime Pro Edition software GUI, as described in the Quartus Prime Pro Edition User Guide, section 1.19.1 Advanced Synthesis Settings. By adding a global assignment in the Quartus project’s QSF file: set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON Resolution To prevent fitter errors during compilation for F-Tile designs, it is essential to preserve the Quartus Tile Logic Generated (QTLG) support logic from being removed by the “Remove Redundant Logic Cells” optimization. This can be achieved by following these steps: Enable global redundant logic optimization for most of the design: set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON Override the setting for the transceiver support logic (Tile IP) to ensure critical blocks are retained: set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF -to top_auto_tiles Note: Replace top_auto_tiles with the actual instance name used in your design. By selectively disabling redundant logic removal for the Tile IP, you safeguard the necessary support logic while optimizing the rest of your design, thereby avoiding fitter errors during compilation. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the Intel® Quartus® Prime Pro Edition Software v21.3 fail to compile in the Support-Logic Generation stages when the design has more than one FGT PMA channel clocked with PMA clocking mode?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.3, if you configure more than one FGT PMA channel with physical medium attachment (PMA) clocking mode in your design, you will run into a known compilation error. This problem happens at the Support-Logic Generation stages during the compilation process. This problem affects the FGT PMA type for both non-return-to-zero (NRZ) and PAM4 mode. FHT PMA type and System PLL clocking mode for FGT PMA are not affected by this problem. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why does my O-RAN Intel® FPGA IP GUI not allow me to turn off “Enable Companding” in the Compression/Decompression dialog box?
Description Due to a problem in the Intel® Quartus® Prime software version 20.2 and later, the O-RAN Intel® FPGA IP has “Enable Companding” in the Compression/Decompression dialog box always turned on. Resolution This problem has been fixed starting with the the Intel® Quartus® Prime software version 20.3Have the Arria® 10 PCI Express* Testbench required simulation files changed in version 24.2 of the Quartus® Prime Design Software?
Description Yes, as part of the ongoing improvements and streamlining of the Quartus® Prime Design Software core device family models (altera_mf etc.) the PCI Express* link-partner root-port BFMs that shipped as part of the altera_pcie_a10_tbed (IP version 19.1) were updated starting in version 24.2 to use Arria® 10 FPGA based primitives rather than the previously used Stratix® II FPGA primitives without a corresponding IP version increase. Attempting to use device libraries compiled from newer versions of Quartus® Prime Design Software with a testbench generated from an older version of the Quartus® Prime Pro software may lead to runtime errors from simulators about invalid module parameters of the form: Error! Unknown INTENDED_DEVICE_FAMILY=Stratix II. Resolution To resolve this problem, it is recommended to always re-generate Altera IP with the same version of the Quartus® Prime Pro software being used.
