Why does the simulation fail for GTS HDMI IP Design Example when running using the Questa* – Altera® FPGA Edition simulator?

Description

When running the simulation in the GTS HDMI IP Design Example using Questa* – Altera® FPGA Edition simulator, the simulation will hang for a long time. This occurs on the integrated PHY design only i.e. when HDMI wrapper option is selected as “HDMI and Transceiver” in the IP GUI.

This is because Questa* – Altera® FPGA Edition does not support altera_pro/<quartus version>/quartus/eda/sim_lib2 library and still uses the older sim_lib library.  On other simulators (such as QuestaSim*), this problem is not observed as they can compile the sim_lib2 library from source. However, Questa-FPGA Edition requires pre-compiled libraries (which is not available).

Resolution

There is no plan to fix this problem.

Altera recommends using another supported third-party simulator.