Why is the I2C Avalon® Memory Mapped FPGA Host Bridge not writing to On-Chip RAM correctly when using Quartus® Prime Pro Edition Software?
Description When using the Avalon® Memory Mapped Host Bridge Core for writing into On-Chip RAM, the data might get lost or incorrectly written into memory. This behavior can be observed when writing a stream of 4 bytes to memory in certain memory offsets, in some cases, the fourth byte will not be written or misplaced into the i2c_avalon_master_address signal. This problem occurs because of the following reasons: A mishandling of an illegal byteenable condition being issued, described in the Altera® FPGA I2C Agent to Avalon Memory Mapped Host Bridge Core > Write Operation documentation. A mishandling of a multiple write burst condition or split write state performed by the Avalon Memory Mapped Host Bridge Core. This problem was found in the Quartus® Prime Pro Edition Software version 19.1 for Linux*. Resolution To overcome the problem, download the Latest Device Firmware for the Quartus® Prime Pro Edition Software version 22.2 from the following knowledge article: https://community.altera.com/kb/knowledge-base/what-is-the-latest-device-firmware-for-the-agilex%c2%ae-fpga-and-stratix%c2%ae10-fpgas/341066 This problem is fixed in the Quartus® Prime Pro Edition Software v22.3 and Quartus® Prime Standard Edition Software v22.1 onwards.
Why does the EMIF and Ethernet IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and 24.3, you might see hold timing violations in Timing Analyzer when using the EMIF and Ethernet IPs. This problem only refers to Agilex™ 7 FPGA devices. Resolution This problem has been resolved in Quartus® Prime Pro Edition Software version 25.3.Why are there minimum pulse width violations in DDR5 Component External Memory Interfaces (EMIF) IP and DDR5 DIMM External Memory Interfaces (EMIF) IP of Agilex™ 7 FPGA M-Series and Agilex™ 5 FPGA D-Series devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, DDR5 Component External Memory Interfaces (EMIF) IP and DDR5 DIMM External Memory Interfaces (EMIF) IP might show minimum pulse width violations. Resolution It is safe to ignore these minimum pulse width violations. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Can LPDDR5 External Memory Interfaces (EMIF) IP support single VDD2 rail mode in Agilex™ 5 FPGA and Agilex™ 7 FPGA M‑Series devices?
Description No. LPDDR5 External Memory Interfaces (EMIF) IP in Agilex™ 5 FPGA and Agilex™ 7 FPGA M‑Series devices only supports dual VDD2 rail mode. Resolution You need to separate VDD2 power at memory device as follows. VDD2H = 1.05V VDD2L = 0.9VWhy does my EMIF IP RDIMM design have invalid assignments for SDA/SCL signals after compilation?
Description Due to a problem in the Quartus® Prime Pro Edition software versions 25.1.1, 25.3, and 25.3.1, the Fitter does not automatically place the I2C SDA/SCL signals when they are not explicitly assigned. Resolution To work around the problem, manually assign legal locations for the following signals on the AC1 lane: SDA: index 10 SCL: index 11 For details, see the “Address and Command Pin Placement” table in the External Memory Interfaces Agilex™ 7 M‑Series FPGA IP User Guide (DDR5): Address and Command Pin Placement. Additional Information Affected Quartus® Prime versions: 25.1.1 25.3 25.3.1 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does the slew rate value become unset after upgrading External Memory Interfaces (EMIF) IP in Agilex™ 7 FPGA F-Series and I-Series devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1 and earlier, the slew rate values in the FPGA I/O tab of External Memory Interfaces (EMIF) IP might change to unset after upgrading the IP to a newer version. Resolution To work around this problem, follow these steps: Toggle the Use default I/O settings checkbox. Change slew rate to desired settings. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.1.Does the Agilex™ 5/3 FPGA HPS EMIF support the External Memory Interface Debug Toolkit?
Description The HPS EMIF controller does support the External Memory Interface Debug Toolkit. Using the following steps, create a design that instantiates the FPGA memory controller using the parameters for the HPS memory interface, and route it to the same I/O that the HPS EMIF uses. Related Information 12.5. Debugging with the External Memory Interface Debug Toolkit 1. Select the HPS EMIF IP within the Platform Designer project. 2. Click Dive Into Packaged Subsystem in the External Memory Interfaces for HPS IP window. 3. In the new window, single-click on the EMIF IP inside the packaged IP window to view the Memory Device parameters on the right side, then click Generate Example Design. 4. Select the directory for the compile design: 5. The example design will be created. NOTE: If the HPS-EMIF is composed of 2 fabric-EMIFs, then the generated example design will only contain 1 fabric-EMIF. NOTE: The Use Debug Toolkit option will be turned on in the generated example design. 6. Save and exit the Dive Into Packaged Subsystem window. Resolution The support will begin in a future release of the Quartus® Prime Pro Edition Software.How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?
Description You can merge multiple EMIF design examples by configuring the required interconnections using Quartus® Prime Platform Designer. This manual process involves setting up and verifying each connection to ensure proper integration. Resolution To streamline and automate the merging of multiple EMIF designs, use the Agilex™ Multiple EMIF Designer Tool (AMED). This tool simplifies the integration process by handling the configuration steps automatically, reducing the potential for errors and saving time. You can download the AMED tool below. Follow the steps below to utilize the AMED tool: Copy all the *.tcl files into the same directory. Open a terminal: On Windows*, open Command Prompt. On Linux*, open Konsole or your preferred terminal. Navigate to the directory containing the *.tcl files using the cd command. Run the script by entering the command: tclsh multi_emif.tcl Navigating the AMED GUI: Select the number of designs to merge. Browse and add each design’s directory path. Set the output directory for the merged design. (Optional) Check Run Analysis & Synthesis to complete this stage automatically. Click Generate to start merging. Additional Information Note: Ensure that you specify the installation paths for standalone Quartus® environments as applicable: For Windows* standalone installation, provide the path, for example: C:/altera_pro/25.1/quartus For Linux* standalone installation, specify the appropriate installation directory path up to the “quartus” folder (e.g., /path/to/quartus). This step is not required when using Network-Based Quartus® installations on Linux*.Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Error (175020): The Fitter cannot place logic IO_LANE that is part of Generic Component ed_synth_phylite_s20_0_example_design, to which it is constrained, because there are no valid locations in the region for logic of this type
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.4, you may encounter a fitter issue while placing REFCLK sharing between IO48 tiles within the same banks in PHY Lite Interfaces Intel Agilex® 7 FPGA IP. Resolution These errors are due to a hardware limitation. The fitter didn't check the REFCLK location constraint because it assumes the REFCLK needs to be in the same tile.
