Why do I see the HPS on Intel Agilex® SoC devices fail to boot, or observe some unexpected functional failures at run time?
Description Due to a problem in the device manager firmware, you might fail to read/write certain RAMs on some Intel Agilex® SoC devices. Impacted HPS RAMs include L2 cache, OCRAM, CCU, USB, CoreSight, and EMAC. You might observe the following HPS boot failures: HPS hangs at dcache memory write and read after executing the dcache_enable function in FSBL UART printout stops after “DDR: 8192 MiB” UART printout stops after “Loading Environment from MMC… ***” UART printout stops after “Verifying Hash Integrity … crc32” Various unexpected functional failures depending on the faulty RAM location Resolution To resolve this problem, update to the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software v21.2, 21.3, 21.4, 22.1, and 22.2. The latest device manager firmware is available from the following link: What is the latest device firmware for Intel Agilex® and Intel® Stratix® 10 devices? This problem is fixed beginning with version 22.4 of the Intel® Quartus® Prime Pro Edition software.Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why isn’t a programming (SOF) file generated for the F-Tile Dynamic Reconfiguration Suite IP available for Example Designs when using the Quartus® Prime Pro Edition software versions 25.3 and earlier?
Description Due to starting from the Quartus® Prime Pro Edition software version 25.3 and earlier, it is compulsory to connect all the I/O ports to the correct PIN location. If any of the design I/O ports are floating and not properly connected, Quartus software will not be able to generate the programming file for the design compiled. This is mentioned in the Quartus Prime Pro Edition User Guide version 25.1.1 in 1.2. Generating Secondary Programming Files and provide the guidelines to the user on how to fix the Quartus software critical warning and successfully create the programming file for your design. Why don’t I get a programming file when I compile with the.... Similar programming (SOF) file generation problem you may observe when you generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting Target Development Kit with option 1) Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4xF-Tile) DK-SI-AGI027FA or 2) Agilex 7™ FPGA I-Series Transceiver-SoC Development Kit (Production 2 4xF-Tile) DK-SI-AGI027FC. As shown in the figure below. Resolution As a workaround, generate the F-Tile Dynamic Reconfiguration Suite IP Example Designs by selecting the Target Development Kit with the option you want and compiling the design. Review the I/O Assignment Warnings report, found in the Place sub-section of the Fitter section of the compilation report. Alternatively, review the <revision>.fit.plan.rpt report file. For any pins in the I/O Assignment Warnings report that are reported as “Missing location assignment” or “Missing I/O standard,” add the appropriate location or I/O standard assignment. For help making these assignments, refer to Assigning I/O Pins. After adding any required assignments, recompile the design to generate a programming file. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.What problems must I know about in the Quartus® Prime Pro Edition Software version 21.2?
Description If you are using the Quartus® Prime Pro Edition Software version 21.2, consider the following important solutions: Resolution Why is the Configuration via Protocol (CvP) Initialization / CvP Update not functioning in Agilex™ 7 F-Tile & R-Tile devices? Why do I see functional errors in hardware when using the Stratix® 10 10GBASE-KR PHY IP core? Why does my Altera® Phylite IP fail in hardware when the VCO is running around 1066 MHz (with Interface frequency around 266/533/1066MHz)? Why does my Agilex™ 7 FPGA tri-state GPIO pin fail in hardware?Why is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the F-Tile Triple-Speed Ethernet IP Design Example fail during simulation on Windows using ModelSim* in the Quartus® Prime Pro Edition Software version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, the F-Tile Triple-Speed Ethernet (TSE) IP Design Example variant - “10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2xTBI PCS with F-Tile FGT Transceiver” - may fail during simulation on Windows platforms using ModelSim*. This problem occurs because the simulation script generated for the design example contains incorrect backslash (“\”) usage, which is not compatible with Windows* path formatting requirements. Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software version 24.3. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench fail to simulate correctly in the supported Siemens* QuestaSim* 2021.4 or later versions?
Description Due to a compatibility problem between version 22.3 and later of the Intel® Quartus® Prime Software and the Siemens* QuestaSim* 2021.4, 2022.4 tool, simulation of the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench will fail to simulation correctly with the following errors: # INFO: 116032 ns RP User Avmm Driver: begin RP Configuration. # FATAL: Simulation stopped due to inactivity! # FAILURE: Simulation stopped due to Fatal error! # FAILURE: Simulation stopped due to error! Resolution To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.Why does design compilation in the Quartus® Prime Pro Edition software version 25.3 and earlier fail during the fitter stage when the “Remove Redundant Logic Cells” option is enabled, and the F-Tile Dynamic Reconfiguration Suite IP is used in the design?
Description Many users enable the “Remove Redundant Logic Cells” option to optimize their designs for area and speed. However, when this Advanced Synthesis setting (REMOVE_REDUNDANT_LOGIC_CELLS) is turned on globally for F-Tile designs —particularly those that include the F-Tile Dynamic Reconfiguration Suite IP— it can inadvertently remove essential support logic (QTLG-generated logic) required for proper transceiver tile operation. As a result, design compilation in the Quartus® Prime Pro Edition software version 25.3 and earlier may fail during the fitter stage with errors related to transceiver logic placement, such as: Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts... Error (175001): The Fitter cannot place 1 HSSI_PLDADAPT_TX. The “Remove Redundant Logic Cells” option can be enabled in two ways: Through the Quartus Prime Pro Edition software GUI, as described in the Quartus Prime Pro Edition User Guide, section 1.19.1 Advanced Synthesis Settings. By adding a global assignment in the Quartus project’s QSF file: set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON Resolution To prevent fitter errors during compilation for F-Tile designs, it is essential to preserve the Quartus Tile Logic Generated (QTLG) support logic from being removed by the “Remove Redundant Logic Cells” optimization. This can be achieved by following these steps: Enable global redundant logic optimization for most of the design: set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON Override the setting for the transceiver support logic (Tile IP) to ensure critical blocks are retained: set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF -to top_auto_tiles Note: Replace top_auto_tiles with the actual instance name used in your design. By selectively disabling redundant logic removal for the Tile IP, you safeguard the necessary support logic while optimizing the rest of your design, thereby avoiding fitter errors during compilation. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why quartus_sign fails to generate a signed ccert for Agilex™ 7 FPGA when running an AES root key provisioning command?
Description When running the quartus_sign command for Agilex™ 7 AES Root Key Provisioning, Quartus® Prime Pro Software fails with Error (20354). Executing the following two commands fails when running the commands below: ## Create an unsigned AES compact certificate for the desired AES root key storage location: quartus_pfg --ccert -o ccert_type=EFUSE_WRAPPED_AES_KEY -o password=passphrase.txt -o qek_file=aes_root.qek unsigned_efuse1.ccert ## Sign the compact certificate with the quartus_sign command or reference implementation: quartus_sign --family=agilex7 --operation=sign --pem=aesccert1_private.pem --qky=aesccert1_sign_chain.qky unsigned_efuse1.ccert signed_efuse1.ccert Resolution You need to set the permission=0x40 when running this command. Full command as below: quartus_sign --family=agilex --operation=append_key \ --previous_pem=root0_private.pem \ --previous_qky=root0.qky \ --permission=0x40 \ --cancel=1 \ --input_pem=aesccert1_public.pem \ aesccert1_sign_chain.qky Additional Information Please refer to Intel Agilex™ 7 FPGA Device Security User Guide page 33 for more details.
