Forum Discussion

EdCz's avatar
EdCz
Icon for New Contributor rankNew Contributor
1 month ago

F-Tile xcvr placement on DK-DEV-AGF023FA

I have an  Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF023F.  I have 1 F-Tile working with PCIe Gen4x16, and want to use the second for 400Gb Ethernet.

I have used the F-Tile channel placement tool, which results in a valid placement. See attached.  

I have been plagued with placer message such as the following.

Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 400g block but the location only supports stream(s) [7, 11, 13, 14].  

I have swapped bit orders and other trials, and they all lead to a similar error.  Given the placement of the QSFPDD on the board, I need to used FGT Quads 2 and 3

I have also tried to use the 100G-4 F-Tile configuration, which move the FGT usage to Quad 1.  And I result it the following error:

Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 100g block but the location only supports stream(s) [1, 2, 3].

I have tried the example design, changing the device to the above board, but the build fails.  Using Quartus 25.3.0

What is needed to move past these errors?

Thanks,  Ed.

9 Replies

  • EdCz's avatar
    EdCz
    Icon for New Contributor rankNew Contributor
    1 month ago

    I have work-around the placement error, by the use of the "Tile Interface Planner"   This has allowed Analysis & Elaboration to complete.  

    Synthesis however fails with the following errors:

    Error(13076): The pin "ftile_eth|u0|eth_f_0|sip_inst|rd_ptr_sync|ml[0].lrm.CLK0[0]" has multiple drivers. 
	Error(20073): "non-tri-state driver "f7aq1a_auto_tiles|z1577b_x3_y166_n0|x0_x0_u25_2_hdpldadapt_pld_pcs_tx_clk_out1_dcm"" is one of the multiple drivers. 
	Error(20073): "non-tri-state driver "f7aq1a_auto_tiles|z1577b_x3_y166_n0|x0_x0_u25_2_hdpldadapt_pld_pma_internal_clk1_hioint"" is one of the multiple drivers.

    This appears to be a Quartus generation error or some IP configuration combination  is not supported.  What is the next step?

     

    • RongY_altera's avatar
      RongY_altera
      Icon for Contributor rankContributor
      1 month ago

      Hi,

      The Quad location should be valid. Please make the clock only for ethernet (or temporary remove PCIe). In the qsf, not use "PRESERVE_UNUSED_XCVR_CHANNEL ON" and set all rx/tx_serial pins explicitly. 

       

      Regards,

      Rong

       

  • EdCz's avatar
    EdCz
    Icon for New Contributor rankNew Contributor
    1 month ago

    Rong,

    Thank you for your suggestions!

    I removed the F-Tile for the PCIe endpoint, and the PRESERVE_UNUSED_XCVR_CHANNEL settings. as suggested.  The multiple-driver error remains.  This  error occurs within the <design>_auto_tiles hierarchy, so there is little I can do address this in my design.

    Are there any other possilble work-arounds?

    Many thanks,
    Ed.

     

     

     

     

    • RongY_altera's avatar
      RongY_altera
      Icon for Contributor rankContributor
      1 month ago

      Error(13076): The pin "ftile_eth|u0|eth_f_0|sip_inst|rd_ptr_sync|ml[0].lrm.CLK0[0]" has multiple drivers.

      >>You need to check this clock. The report says it is driven by multiple sources. 

      >>You can also generate a 400G example design as a reference to confirm your clock connections.

       

      Regards,

      Rong

      • EdCz's avatar
        EdCz
        Icon for New Contributor rankNew Contributor
        1 month ago

        The multiple clock error is deep inside of a hierarchy generated by Quartus.  I have tried many configurations of the F-Tile and its clocking IP, but without success.  

        As for the 400G example design, while I can generate an example design, Quartus does not support the F-Series Development Kit 2xF-Tile DK-DEV-AGF023F. as a target device.  Since I can successfully compile for other devices, I am assuming my configurations are correct.

        This is blocking our use of the dual- F-Tile device for ethernet.  Are you able to generate a 400G Ethernet for the 2xF-Tile dev kit?

        Thanks, Ed.

  • EdCz's avatar
    EdCz
    Icon for New Contributor rankNew Contributor
    1 month ago

    Yes,  The 400G uses the FGT Quad2 and Quad 3 (Bank 12C), with the ref clock #6 as REFCLK_FGTL12C_Q3_RX_CH6P.  The schematic calls this out very nicely on page 20. I am able to verify these assignment with the Tile Interface Planner.  

    Ed.

    • RongY_altera's avatar
      RongY_altera
      Icon for Contributor rankContributor
      1 month ago

      Using Q24.3.1 Pro to generate a FGT 400Gx8 example design and do migration to your target Dev Kit. The project can pass compilation. 

       

      I suggest you create the example design based on the current Quartus version you're using, rather than upgrading a project created by another version.

       

       

       

       

       

      Regards,

      Rong

       

    • RongY_altera's avatar
      RongY_altera
      Icon for Contributor rankContributor
      1 month ago

       

      Pasting full qsf will cause error. Here are the pins.

       

      set_location_assignment PIN_CK18 -to i_reconfig_clk
      set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to i_reconfig_clk
      set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to i_reconfig_clk

      set_location_assignment PIN_AD48 -to i_refclk2pll
      set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to i_refclk2pll


      set_location_assignment PIN_R49 -to o_tx_serial[0]
      set_location_assignment PIN_V52 -to o_tx_serial[1]
      set_location_assignment PIN_W49 -to o_tx_serial[2]
      set_location_assignment PIN_AB52 -to o_tx_serial[3]
      set_location_assignment PIN_AF52 -to o_tx_serial[4]
      set_location_assignment PIN_AK52 -to o_tx_serial[5]
      set_location_assignment PIN_AP52 -to o_tx_serial[6]
      set_location_assignment PIN_AV52 -to o_tx_serial[7]
      set_location_assignment PIN_K52 -to i_rx_serial[0]
      set_location_assignment PIN_P52 -to i_rx_serial[1]
      set_location_assignment PIN_R55 -to i_rx_serial[2]
      set_location_assignment PIN_W55 -to i_rx_serial[3]
      set_location_assignment PIN_AC55 -to i_rx_serial[4]
      set_location_assignment PIN_AG55 -to i_rx_serial[5]
      set_location_assignment PIN_AL55 -to i_rx_serial[6]
      set_location_assignment PIN_AR55 -to i_rx_serial[7]
      set_location_assignment PIN_T48 -to o_tx_serial_n[0]
      set_location_assignment PIN_U51 -to o_tx_serial_n[1]
      set_location_assignment PIN_Y48 -to o_tx_serial_n[2]
      set_location_assignment PIN_AA51 -to o_tx_serial_n[3]
      set_location_assignment PIN_AE51 -to o_tx_serial_n[4]
      set_location_assignment PIN_AJ51 -to o_tx_serial_n[5]
      set_location_assignment PIN_AN51 -to o_tx_serial_n[6]
      set_location_assignment PIN_AU51 -to o_tx_serial_n[7]
      set_location_assignment PIN_J51 -to i_rx_serial_n[0]
      set_location_assignment PIN_N51 -to i_rx_serial_n[1]
      set_location_assignment PIN_T54 -to i_rx_serial_n[2]
      set_location_assignment PIN_Y54 -to i_rx_serial_n[3]
      set_location_assignment PIN_AD54 -to i_rx_serial_n[4]
      set_location_assignment PIN_AH54 -to i_rx_serial_n[5]
      set_location_assignment PIN_AM54 -to i_rx_serial_n[6]
      set_location_assignment PIN_AT54 -to i_rx_serial_n[7]

       

      set_global_assignment -name DEVICE AGFD023R24C2E1VC
      #set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON