Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted

Where can I find any public available dev kit design example for the Agilex3 or Agilex which can implement the GTS Eth HIP as generated by Quartus Pro v25.3 and successfully build a sof file?

A set of pin locations and IO standard settings for the AXE5 Eagle would be optimal, but any other dev kit would be helpful.

According to the "GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs" (848477) page 29 under "Target Development Kit Tab" is says:

"Target development kit option specifies the target development kit used to generate the project. Ensure the pin assignments in the .qsf file are appropriate."

But it seems like this will only set the BOARD parameter in the resulting qsf, e.g. when using the Premium Development Kit it results in the following addtion to the qsf file:

set_global_assignment -name BOARD "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1"

which results in no location or IO standard settings in the qsf and I/O Assignment Warnings in the fitter report after the build:

+-----------------------------------------------------------------------------------------------------------------------+

; I/O Assignment Warnings ;

+-----------------------+-----------------------------------------------------------------------------------------------+

; Pin Name ; Reason ;

+-----------------------+-----------------------------------------------------------------------------------------------+

; o_tx_serial_data[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ;

; o_tx_serial_data_n[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ;

; qsfp_lowpwr ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ;

; qsfp_rstn ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ;

; i_reconfig_clk ; Missing I/O standard ;

; i_rx_serial_data_n[0] ; Missing I/O standard ;

; i_rx_serial_data[0] ; Missing I/O standard ;

; i_clk_ref_p ; Missing I/O standard ;

; o_tx_serial_data[0] ; Missing location assignment ;

; o_tx_serial_data_n[0] ; Missing location assignment ;

; qsfp_lowpwr ; Missing location assignment ;

; qsfp_rstn ; Missing location assignment ;

; i_reconfig_clk ; Missing location assignment ;

; i_rx_serial_data_n[0] ; Missing location assignment ;

; i_rx_serial_data[0] ; Missing location assignment ;

; i_clk_ref_p ; Missing location assignment ;

; i_refclk2pll_p ; Missing location assignment ;

+-----------------------+-----------------------------------------------------------------------------------------------+

Whenever I try to assign these myself I get errors like

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IPFLUXTOP_UXTOP_WRAP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.

Error (175001): The Fitter cannot place 1 IPFLUXTOP_UXTOP_WRAP, which is within GTS Ethernet Hard IP ex_10G_intel_eth_gts_1000_6dyx4dq.

or this or other type of layout or clocking type constraint errors:

Error (11216): Output port "O_SYSPLL_C0" of "SM_HSSI_PLL_WRAP" cannot connect to PLD port "CLK" of "FF" for node "kr_dut|intel_eth_anlt_gts_0|ip_inst|sip_inst|u_intel_eth_anlt_gts_csr_top|u__intel_eth_anlt_gts_csr_avmm_arb|o_avmm_rdata[0]".

It would be nice if I could obtain a set of correct and working pin assignment which actually results in a working sof file so I can try to understand what the actual constraints are.

Is there a dev kit as described which the pin assignments are generated or provided or could anybody please provide a set of pin assignments for the above signals for a dev kit?

Cheers!