Occasional Contributor
Occasional ContributorI did not set the board to None. In my message above I said that I sat it to the Premium Development Kit and this resulted only one extra setting, i.e. the BOARD variable in the resulting QSF file as I explained above.
However, if I build the design it will not generate a sof file, but the resulting pin file will have some default assignments which can be back annotated into the QSF.
What I would like to obtain is some QSF pin locations and IO standard settings for the GTS 10G ethernet hard IP example design for the AXE5 Eagle development kit. It would be great if anybody knows where I can find these?
Frequent ContributorHello,
Apologies for the confusion.
I believe this would help you :https://github.com/ArrowElectronics/ghrd-socfpga/
Regards,
Pavee
Occasional ContributorThank you Pavee, that is one of the sources I've been using as well as the schematics and user guide for the dev kit. Still I have not yet been able to build a working version of the GTS Hard Ethernet IP 10G example design on the Eagle board.
New ContributorHi Zener
The recently released Quartus Pro 26.1 creates a 10G example design with pin assignments for the Agilex 5 Premium Dev Kit This example design successfully builds and creates a SOF.
See GTS Ethernet Hard IP User Guide Agilex™ 5 FPGAs and SoCs for details on this example as well as details on how to simulate and run the example in HW using the provided System Console files.
Perhaps you can map the Eagle board pin out to this example design.
I hope this helps.
Best,
Bob
Frequent ContributorWe do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get the support from Altera experts.
Otherwise, the community users will continue to help you on this thread.
Thank you.
