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zener's avatar
zener
Icon for Occasional Contributor rankOccasional Contributor
5 months ago

Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted

Where can I find any public available dev kit design example for the Agilex3 or Agilex which can implement the GTS Eth HIP as generated by Quartus Pro v25.3 and successfully build a sof file? A set ...
Ethernet
Transceiver
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
5 months ago

Hello Zener,

 

The example design does not include pin location or I/O standard assignments when “board = None” is selected. This is expected because the GTS Ethernet Hard IP relies on fixed transceiver resources, which must be mapped based on the target hardware.

To resolve this, use a dev kit example as reference.

Agilex 5: https://docs.altera.com/r/docs/817676/25.1.1/gts-ethernet-hard-ip-user-guide-agilextm-5-fpgas-and-socs/generate-gts-ehip-design-example

Agilex 3:  https://docs.altera.com/r/docs/848477/25.1.1/gts-ethernet-hard-ip-user-guide-agilextm-3-fpgas-and-socs/generate-gts-ehip-design-example

 

Regards,

Pavee