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I did not set the board to None. In my message above I said that I sat it to the Premium Development Kit and this resulted only one extra setting, i.e. the BOARD variable in the resulting QSF file as I explained above.
However, if I build the design it will not generate a sof file, but the resulting pin file will have some default assignments which can be back annotated into the QSF.
What I would like to obtain is some QSF pin locations and IO standard settings for the GTS 10G ethernet hard IP example design for the AXE5 Eagle development kit. It would be great if anybody knows where I can find these?
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