JESD204B Multi-Link Implementation with AD9695 ADCs Having Different Lane Counts (L=4 and L=2)

Hello Intel Community,

I am currently working on a multi-chip ADC design using the AD9695 with the JESD204B interface on an Intel Stratix 10 FPGA. I am using the JESD204B Intel FPGA IP core and have been referring to the example design provided with the IP. I have also followed the guidelines mentioned in Intel Application Note AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel Stratix 10 JESD204B RX IP Core.

In my design, I have three ADC chips with the following configuration:

• ADC 1: 4 lanes (L=4)
• ADC 2: 4 lanes (L=4)
• ADC 3: 2 lanes (L=2)

All other JESD204B parameters (such as F, M, S, N, N') are identical across all three ADCs.

According to AN 804, it is mentioned that when adding multiple subsequent links within a single JESD204B IP core, all links must share the same set of JESD parameters, including the number of lanes (L). Since my third ADC has a different lane count, I am unsure about the correct implementation approach.

I would appreciate your guidance on the following:

1. Can I integrate all three ADCs into a single JESD204B IP core instance by configuring it as a multi-link design, even though the lane counts differ?
2. If not, should I instantiate three separate JESD204B IP cores, each configured as a single link (L=4, L=4, L=2 respectively)?
3. Alternatively, should I instantiate two IP cores — one for the first two ADCs (with L=4, using the multi-link feature) and a second core for the third ADC (with L=2)?

Could you please suggest the correct and most efficient path forward? Also, if I use separate IP cores, what are the key considerations for ensuring proper synchronization (Subclass 1) and reliable operation across all three links?

Any insights, reference designs, or best practices would be greatly appreciated.

Thank you in advance for your support.

Best regards,
BALAMURuGAN V