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VBalamurugan29's avatar
VBalamurugan29
Icon for New Contributor rankNew Contributor
2 months ago

JESD204B Multi-Link Implementation with AD9695 ADCs Having Different Lane Counts (L=4 and L=2)

Hello Intel Community,

I am currently working on a multi-chip ADC design using the AD9695 with the JESD204B interface on an Intel Stratix 10 FPGA. I am using the JESD204B Intel FPGA IP core and have been referring to the example design provided with the IP. I have also followed the guidelines mentioned in Intel Application Note AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel Stratix 10 JESD204B RX IP Core.

In my design, I have three ADC chips with the following configuration:

  • ADC 1: 4 lanes (L=4)
  • ADC 2: 4 lanes (L=4)
  • ADC 3: 2 lanes (L=2)

All other JESD204B parameters (such as F, M, S, N, N') are identical across all three ADCs.

According to AN 804, it is mentioned that when adding multiple subsequent links within a single JESD204B IP core, all links must share the same set of JESD parameters, including the number of lanes (L). Since my third ADC has a different lane count, I am unsure about the correct implementation approach.

I would appreciate your guidance on the following:

  1. Can I integrate all three ADCs into a single JESD204B IP core instance by configuring it as a multi-link design, even though the lane counts differ?
  2. If not, should I instantiate three separate JESD204B IP cores, each configured as a single link (L=4, L=4, L=2 respectively)?
  3. Alternatively, should I instantiate two IP cores — one for the first two ADCs (with L=4, using the multi-link feature) and a second core for the third ADC (with L=2)?

Could you please suggest the correct and most efficient path forward? Also, if I use separate IP cores, what are the key considerations for ensuring proper synchronization (Subclass 1) and reliable operation across all three links?

Any insights, reference designs, or best practices would be greatly appreciated.

Thank you in advance for your support.

Best regards,
BALAMURuGAN V

Jesd
Transceiver

4 Replies

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      2 months ago

      Hi,

       

      Thank you for filing this case and sharing the details. Sorry as I might have overlooked this. Please allow me some time to look into your queries and get back to you. Thank you.

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      2 months ago

      Hi,

       

      Just to follow up if there is any inquiry. Thank you.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi,

     

    My understanding is that you are using the JESD204B RX IP to interface with three ADCs, with link configurations of L=4, L=4, and L=2.

     

    Since there are 3 ADCs, the most robust implementation would be to instantiate three separate single-link JESD204B RX IP cores.

     

    For proper Subclass 1 synchronization and reliable operation across the three links, please consider the following:

    1. Maintain a common SYSREF and device-clock scheme across the FPGA and all ADCs, with careful trace matching and minimal SYSREF phase offset. 
    2. Keep SYNC~ handling aligned across all three links. In multi-link synchronization schemes, the DEV_SYNC_N signals from the IP cores can be combined as described in the JESD204B guidance. 
    3. Ensure the link clock and frame clock remain synchronous through the selected transceiver PLL and clocking architecture.

     

    Overall, using separate IP instances is the safest and most straightforward approach for this configuration.

    Thank you.