F-Tile PCIe Root port - rx_st_hdr_o

Hello,

Reading the F-Tile Avalon Streaming IP for PCIExpress User Guide , UG-20331 2026.02.11.  In X4 configuration, the 'rx_st_hrd_o(127:0)' signals is valid when 'rx_st_sop'=1 and rx_st_valid_o'=1, is is correct ?

If Yes, it means that even for just a Memory Read Command Data the 'rx_st_data_o(127:0)' signals are valid as well, correct ? If yes this data has to be ignored ?

If not, please provide detail explanation about the validity of the 'rx_st_hrd_o(127:0)'.

Thanks for help.
Serge