Cyclone 10 GX Transceiver Power-Up Calibration Time (~353 ms) Analysis Request

We are observing a transceiver power-up calibration time of approximately 353 ms on a Cyclone 10 GX device (10CX220YF780I6G) using all 12 transceivers.

The total system startup requirement is 250 ms (configuration + calibration + system boot constraints), and the calibration phase alone is currently a limiting factor.

According to the Cyclone 10 GX Transceiver PHY User Guide, calibration is performed automatically during device configuration via the PreSICE engine and is dependent on reference clock stability, PLL lock conditions, and reset controller sequencing.

The documentation does not specify a deterministic calibration duration.

Please can you provide clarification on the following points:

• Is a ~353 ms calibration time expected behavior for a design using all 12 transceivers on this device family?
• Is transceiver calibration executed sequentially across multiple quads, or is full parallel calibration supported for all active transceiver banks in Cyclone 10 GX?
• Are there any recommended design practices (reset controller configuration, PLL topology, clocking architecture) that can reduce power-up calibration latency?
• Can calibration duration be significantly impacted by reference clock stabilization time or internal wait states prior to PreSICE execution?

The goal is to determine whether the observed latency is inherent to the device architecture or if it can be optimized at system level.