Forum Discussion
New ContributorFitter Error with Clock Switchover Enabled in Altera PLL (Normal Mode)
Hi everyone,
I ran into the following Fitter Error when enabling Clock Switchover on an Altera PLL in Normal mode:
- Error (14996): The Fitter failed to find a legal placement for all periphery components
- Info (14987): The following components had the most difficulty being legally placed:
- Info (175029): fractional PLL altera_pll_blk:u0|altera_pll_blk_0002:altera_pll_blk_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|altera_arriav_pll_base:fpll_0|fpll (100%)
- Error (14986): After placing as many components as possible, the following errors remain:
- Error (175001): The Fitter cannot place 1 fractional PLL, which is within PLL Intel FPGA IP altera_pll_blk.
- Info (14596): Information about the failing component(s):
- Info (175028): The fractional PLL name(s): altera_pll_blk:u0|altera_pll_blk_0002:altera_pll_blk_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|altera_arriav_pll_base:fpll_0|fpll
- Error (16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below:
- Error (12349): Fitter was unable to route the far global PLL feedback path for the fractional PLL (2 locations affected)
- Info (175029): FRACTIONALPLL_X97_Y31_N0
- Info (175029): FRACTIONALPLL_X97_Y40_N0
- Info (175013): The fractional PLL is constrained to the region (97, 30) to (97, 47) due to related logic
- Info (175015): The I/O pad CLKIN is constrained to the location PIN_N2 due to: User Location Constraints (PIN_N2)
- Info (14709): The constrained I/O pad is contained within a pin, which drives this fractional PLL
- Error (12349): Fitter was unable to route the far global PLL feedback path for the fractional PLL (2 locations affected)
- Info (14596): Information about the failing component(s):
- Error (175001): The Fitter cannot place 1 fractional PLL, which is within PLL Intel FPGA IP altera_pll_blk.
- Info (14987): The following components had the most difficulty being legally placed:
Quartus Info
- Quartus Prime Standard Edition v25.1
- Device: Arria V ( 5AGXBA1D4F27C4 )
PLL IP Settings
- [ General ] tab
- PLL Mode: Integer-N PLL
- Operation Mode: Normal
- Feedback Clock: Global Clock
- [ Clock Switchover ] tab
- Automatic Switchover with Manual Override
Pin Assignments
- CLK50M → PIN_M1 (BANK 5A) — refclk1 ( Secondary clock for Clock Switchover )
- CLKIN → PIN_N2 (BANK 5A) — refclk ( Primary clock for Clock Switchover )
Sample Design
- top_module_a5_lvds_rx_Qstd_ver251NG.qar
When I change the PLL mode from Normal to Direct, the Fitter Error disappears and the design compiles successfully. However, in Direct mode, phase compensation is not applied, so I’d prefer to stick with Normal mode.
Question:
What could be the root cause of this Fitter Error in Normal mode, and how can I resolve it while:
・ Keeping Normal mode
・ Keeping the current pin assignments
Any guidance or workaround would be greatly appreciated. Thanks!
4 Replies
Ash_R_AlteraRegular Contributor
Hi,
Thanks for the design. I am able to reproduce the issue. Till now I could figure out that the issue is mainly due to the location which you are trying to use. If I disable the pin constraints and let the tool allocate it, is goes through the compilation. With this first thing that I would like to check with you is whether the input clock pin constraints are hard requirement for you or there is a flexibility to move to some other pins.
Let me know please.
Regards
- Ash_R_Altera
Hi,
Do you have any further comment on my previous ask if there is a room for change in pin assignments?
Regards
Praxis_KernfeldHi Ash,
Thank you for taking the time to reproduce the issue.
There is an important point I should have mentioned earlier.
The behavior you pointed out - "there is a flexibility to move to some other pins" - was something I had already confirmed on my side.
My apologies for not sharing this in my first post.
1. Behavior confirmed beforehand
With the following pin assignment, I had confirmed that the PLL was fitted into FRACTIONALPLL_X0_Y9 within the PLL strip:
- PLL Switchover Primary Clock: PIN_AF21 (clk2p @ BANK 3A)
- PLL Switchover Secondary Clock: PIN_AF20 (clk3p @ BANK 3A)
2. Why I cannot change the current pin assignment
On the target board, the wiring is already fixed as follows, so changing the pin assignment is not an option:
- PLL Switchover Primary Clock: PIN_N2 (clk15p @ BANK 5A)
- PLL Switchover Secondary Clock: PIN_M1 (clk14p @ BANK 5A)
3. Workaround using External Feedback Mode
When I changed the PLL Operation Mode from Normal Mode to External Feedback Mode, Fitting succeeded while keeping the current pin assignment.
Although this requires two additional User I/O pins (fbclk / fboutclk), they can be mapped to unused pins to useable on the board, which I plan to connect using jumper wires as a temporary solution.
In this case, the PLL was fitted into FRACTIONALPLL_X97_Y40.
4. Additional finding
Further isolation showed that the same error occurs even in a simple design using Normal Mode (with Clock Switchover disabled).
With the Reference Clock assigned only to PIN_N2 (BANK 5A), routing resources seem sufficient; however, as the error message suggests,
the Fitter appears to be trying to route the PLL feedback path across two different PLL locations( FRACTIONALPLL_X97_Y40 and FRACTIONALPLL_X97_Y31) .
Error (12349): Fitter was unable to route the far global PLL feedback path for the fractional PLL (2 locations affected)
Info (175029): FRACTIONALPLL_X97_Y31_N0
Info (175029): FRACTIONALPLL_X97_Y40_N0
Questions
Q2.
Apart from changing to External Feedback Mode or modifying the pin assignment (your suggestion), are there any other effective solutions for this issue?
Q3.
In a simple Normal Mode PLL design (Clock Switchover disabled), why does the Fitter attempt to route the PLL feedback path across two PLL locations( FRACTIONALPLL_X97_Y40 and FRACTIONALPLL_X97_Y31) ?
Understanding the root cause will help me gain a clearer view of this error.
I would greatly appreciate your advice.
- Ash_R_Altera
Hi,
I am opening an internal ticket to get help from engineering team on the root cause. It will take time to get a reply for them. I will update you as soon as I get a relevant response.
Regards
