Fitter Error with Clock Switchover Enabled in Altera PLL (Normal Mode)

Hi everyone,

I ran into the following Fitter Error when enabling Clock Switchover on an Altera PLL in Normal mode:

• Error (14996): The Fitter failed to find a legal placement for all periphery components
  • Info (14987): The following components had the most difficulty being legally placed:
    • Info (175029): fractional PLL altera_pll_blk:u0|altera_pll_blk_0002:altera_pll_blk_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|altera_arriav_pll_base:fpll_0|fpll (100%)
  • Error (14986): After placing as many components as possible, the following errors remain:
    • Error (175001): The Fitter cannot place 1 fractional PLL, which is within PLL Intel FPGA IP altera_pll_blk.
      • Info (14596): Information about the failing component(s):
        • Info (175028): The fractional PLL name(s): altera_pll_blk:u0|altera_pll_blk_0002:altera_pll_blk_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|altera_arriav_pll_base:fpll_0|fpll
      • Error (16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below:
        • Error (12349): Fitter was unable to route the far global PLL feedback path for the fractional PLL (2 locations affected)
          • Info (175029): FRACTIONALPLL_X97_Y31_N0
          • Info (175029): FRACTIONALPLL_X97_Y40_N0
        • Info (175013): The fractional PLL is constrained to the region (97, 30) to (97, 47) due to related logic
          • Info (175015): The I/O pad CLKIN is constrained to the location PIN_N2 due to: User Location Constraints (PIN_N2)
          • Info (14709): The constrained I/O pad is contained within a pin, which drives this fractional PLL

Quartus Info

• Quartus Prime Standard Edition v25.1
• Device: Arria V ( 5AGXBA1D4F27C4 )

PLL IP Settings

•  [ General ] tab
  •  PLL Mode: Integer-N PLL
  • Operation Mode: Normal
  • Feedback Clock: Global Clock
• [ Clock Switchover ] tab
  • Automatic Switchover with Manual Override

Pin Assignments

• CLK50M → PIN_M1 (BANK 5A) — refclk1 ( Secondary clock for Clock Switchover )
• CLKIN → PIN_N2 (BANK 5A) — refclk ( Primary clock for Clock Switchover )

Sample Design

• top_module_a5_lvds_rx_Qstd_ver251NG.qar

When I change the PLL mode from Normal to Direct, the Fitter Error disappears and the design compiles successfully. However, in Direct mode, phase compensation is not applied, so I’d prefer to stick with Normal mode.

Question:

What could be the root cause of this Fitter Error in Normal mode, and how can I resolve it while:

・ Keeping Normal mode

・ Keeping the current pin assignments

Any guidance or workaround would be greatly appreciated. Thanks!