Fitter Error with Clock Switchover Enabled in Altera PLL (Normal Mode)

Hi Ash,

Thank you for taking the time to reproduce the issue.

There is an important point I should have mentioned earlier.

The behavior you pointed out - "there is a flexibility to move to some other pins" - was something I had already confirmed on my side.

My apologies for not sharing this in my first post.

1. Behavior confirmed beforehand

With the following pin assignment, I had confirmed that the PLL was fitted into FRACTIONALPLL_X0_Y9 within the PLL strip:

• PLL Switchover Primary Clock: PIN_AF21 (clk2p @ BANK 3A)
• PLL Switchover Secondary Clock: PIN_AF20 (clk3p @ BANK 3A)

2. Why I cannot change the current pin assignment

On the target board, the wiring is already fixed as follows, so changing the pin assignment is not an option:

• PLL Switchover Primary Clock: PIN_N2 (clk15p @ BANK 5A)
• PLL Switchover Secondary Clock: PIN_M1 (clk14p @ BANK 5A)

3. Workaround using External Feedback Mode

When I changed the PLL Operation Mode from Normal Mode to External Feedback Mode, Fitting succeeded while keeping the current pin assignment.

Although this requires two additional User I/O pins (fbclk / fboutclk), they can be mapped to unused pins to useable on the board, which I plan to connect using jumper wires as a temporary solution.

In this case, the PLL was fitted into FRACTIONALPLL_X97_Y40.

4. Additional finding

Further isolation showed that the same error occurs even in a simple design using Normal Mode (with Clock Switchover disabled).

With the Reference Clock assigned only to PIN_N2 (BANK 5A), routing resources seem sufficient; however, as the error message suggests,

the Fitter appears to be trying to route the PLL feedback path across two different PLL locations( FRACTIONALPLL_X97_Y40 and FRACTIONALPLL_X97_Y31) .

Error (12349): Fitter was unable to route the far global PLL feedback path for the fractional PLL (2 locations affected)

Info (175029): FRACTIONALPLL_X97_Y31_N0

Info (175029): FRACTIONALPLL_X97_Y40_N0

Questions

Q2.

Apart from changing to External Feedback Mode or modifying the pin assignment (your suggestion), are there any other effective solutions for this issue?

Q3. 

In a simple Normal Mode PLL design (Clock Switchover disabled), why does the Fitter attempt to route the PLL feedback path across two PLL locations( FRACTIONALPLL_X97_Y40 and FRACTIONALPLL_X97_Y31) ?

Understanding the root cause will help me gain a clearer view of this error.

I would greatly appreciate your advice.