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RZhen11's avatar
RZhen11
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Arria 10 Transceiver rx_cal_busy always HIGH for 24s after programming

Troubleshooting 10G link native, the external TX is always ON. USRCLK 100MHz always ON.

Every time the FPGA is loaded through JTAG or cold boot, there is a 24sec something wait until rx_clk_busy goes to LOW then the link starts functioning normal.

According to Google AI, transceiver calibration module seems got stuck, and unfrozen by hardware watchdog to prevent brick.

We has a different product that establishes link almost immediately with the same transmitter.

Please suggest, thanks

Transceiver

4 Replies

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi,

    I am referring to the following section of the Arria 10 transceiver PHY UG, https://docs.altera.com/r/docs/683617/21.1/arria-10-transceiver-phy-user-guide/power-up-calibration

    As per this, the power-up calibration has a sequence and RX PMA channel calibration almost comes at the end of it. Eventually the rx_cal_busy de-assertion will depends upon the whether the previous blocks i.e. ATX PLL and fPLL calibration are completed or not and whether the PCIe hard IP is enabled or not.

    If the PLLs are taking long, check the input reference clocks to it.

     

    Regards

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Dear Customer,

    I hope that your issue is resolved. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

    Thank you for engaging with us!

    Best regards,
    Altera Technical Support

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Dear Customer,

    I assume that your issue is resolved. If there are no further inquiries the community will be able to assist with any future follow-up questions.

    Thank you for engaging with us!

    Best regards,
    Altera Technical Support

  • RZhen11's avatar
    RZhen11
    Icon for Occasional Contributor rankOccasional Contributor
    2 months ago

    For the record, a short summary:

    The design has: 16 Rx at 2Gbps, 5 Tx + 1 Rx at 10Gbps. One of the 2Gbps Rx(s) was paired with one 10Gbps Tx.

    The 16 Rx(s) were generated as 2 x 8 Transceiver PHY core with 2 reset controller cores.

    After confirming all clock source, and playing with system debugger, I was unable to resolve the issue. Then I deleted the 16 Rx 2Gbps channels all together, and started rebuilding the project. The issue was gone, after one channel recreation. No more issue after using for loop to generate all 16 Transceiver PHY + 16 Reset Controller.

    My suspicion of the root cause is either the 8 in one core is somehow corrupted, or the coding style is not liked by the 23.1 Standard Edition.

    That's it.

    Thanks for your attention