Forum Discussion
RZhen11
Occasional Contributor
2 months agoArria 10 Transceiver rx_cal_busy always HIGH for 24s after programming
Troubleshooting 10G link native, the external TX is always ON. USRCLK 100MHz always ON. Every time the FPGA is loaded through JTAG or cold boot, there is a 24sec something wait until rx_clk_busy goe...
RZhen11
Occasional Contributor
2 months agoFor the record, a short summary:
The design has: 16 Rx at 2Gbps, 5 Tx + 1 Rx at 10Gbps. One of the 2Gbps Rx(s) was paired with one 10Gbps Tx.
The 16 Rx(s) were generated as 2 x 8 Transceiver PHY core with 2 reset controller cores.
After confirming all clock source, and playing with system debugger, I was unable to resolve the issue. Then I deleted the 16 Rx 2Gbps channels all together, and started rebuilding the project. The issue was gone, after one channel recreation. No more issue after using for loop to generate all 16 Transceiver PHY + 16 Reset Controller.
My suspicion of the root cause is either the 8 in one core is somehow corrupted, or the coding style is not liked by the 23.1 Standard Edition.
That's it.
Thanks for your attention