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RZhen11
Occasional Contributor
Occasional ContributorArria 10 Transceiver rx_cal_busy always HIGH for 24s after programming
Troubleshooting 10G link native, the external TX is always ON. USRCLK 100MHz always ON. Every time the FPGA is loaded through JTAG or cold boot, there is a 24sec something wait until rx_clk_busy goe...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
I am referring to the following section of the Arria 10 transceiver PHY UG, https://docs.altera.com/r/docs/683617/21.1/arria-10-transceiver-phy-user-guide/power-up-calibration
As per this, the power-up calibration has a sequence and RX PMA channel calibration almost comes at the end of it. Eventually the rx_cal_busy de-assertion will depends upon the whether the previous blocks i.e. ATX PLL and fPLL calibration are completed or not and whether the PCIe hard IP is enabled or not.
If the PLLs are taking long, check the input reference clocks to it.
Regards
