New ContributorArria 10 DDR4 IP - Using Hyperlynx DDRx Batch Wizard With Failed Simulation Results
Hello,
Device: 10AX066K2F40E1HG
We are designing a DDR4 LRDIMM interface for the above device using the EMIF IP.
We have a board layout, and we are attempting to complete simulation to verify the PCB. We have been using this guide for simulation:
https://community.intel.com/t5/FPGA-Wiki/Arria-10-EMIF-Simulation-Guidance/ta-p/735201
Under the "System-level timing closure" heading, we see the following statement:
"Note: Please do not use any simulation tool to perform system-level timing closure. Use simulation software to obtain channel loss and board skew data. Quartus will close the system level timing for you once you have entered accurate Memory Timing and Board timing information in the IP."
We are using Hyperlynx to extract the channel loss/crosstalk values used for the Quartus IP parameters. Our issue is that some of the nets (BA0, ODT0 specifically), are failing timing in the Hyperlynx DDRx batch wizard. Due to these failures which I have chosen to ignore following the above quote, the Channel Loss Calculation Tool from the Simulation Guidance is failing (I have already worked with Mentor Graphics on this, we are certain that the failing nets (ODT, BA0) are causing the excel channel loss tool to fail). If we delete the failing net rows from the DDRx Wizard results, then the channel loss tool completes.
My question is: Should I be ignoring the timing failures from Hyperlynx, relying on the Arria 10 IP to close the timing? If so, how do I properly pass the DDRx batch results through the calculation tool such that I get good results?
Note: The example data given with the calculation tool have no failing nets, indicating that all nets passed the Hyperlynx DDRx Wizard at the time they were produced.
Attached is the DDR report from the Hyperlynx Batch Wizard. Inside there is a .exe file which will open an explorer for the simulation results. The failed lines can be seen on the address tab.
