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ConnorSousa's avatar
ConnorSousa
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3 years ago

Arria 10 DDR4 IP - Using Hyperlynx DDRx Batch Wizard With Failed Simulation Results

Hello, Device: 10AX066K2F40E1HG We are designing a DDR4 LRDIMM interface for the above device using the EMIF IP. We have a board layout, and we are attempting to complete simulation to verify...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi ConnorSousa,


May I know if there is any question or update regarding to this thread?


Regards,

Adzim


  • ConnorSousa's avatar
    ConnorSousa
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    3 years ago

    I have already gone through the guidelines and I have already worked with Mentor Support regarding the Hyperlynx side. I believe my original question addresses the problem most accurately, so if any thorough investigation is to be done, I believe my original question is the best place to start.

    On my end, we have already decided to move forward with fabricating our PCB. We used manual eye diagram simulation and static geometry analysis to ensure we complied with the guidelines of our particular device, so we were at least somewhat confident in ignoring the Hyperlynx+Channel loss tool combination as described in the guides. Fundamentally, it seems like having an LRDIMM with two ODT control inputs but only one ODT output on the FPGA (memory controller) is the major source of our headache. I don't believe the Hyperlynx DDRx batch wizard supports LRDIMMs directly, nor the special case I just mentioned.

    Thanks,