Arria 10 DDR4 IP - Using Hyperlynx DDRx Batch Wizard With Failed Simulation Results

Adzim,

I did follow the guide you posted. I am concerned that the Channel Loss Calculation Tool is unable to handle signals that did not pass timing during the Hyperlynx DDRx Batch process, but we are told that we should not expect our simulation software to close timing.

How am I able to tell how bad the failed Hyperlynx timing is? Surely the DDR4 IP cannot close any arbitrary timing violation, so what is the actual usable range?

I can simply remove the failed signals from the simulation data and run the Channel Loss tool, but am I potentially making some wrong assumptions in doing so.

Hi,

I am trying to find documentation on how to use the Channel Loss Calculation Tool for Arria 10 DDR4 EMIF.

The "Arria 10 EMIF Simulation Guidance" link referenced above appears to be unavailable/redirected, and I cannot find the document on the current Altera website.

Could you please provide an updated link or any documentation related to the Channel Loss Calculation Tool?

Thanks.