New Contributor
Regular ContributorHi ConnorSousa,
Thank you for submitting your question in Intel Community.
I'm Adzim, application engineer will assist you in this thread.
You can refer to Arria 10 simulation guidance flow to simulate the board simulation.
Link: https://community.intel.com/t5/FPGA-Wiki/Arria-10-EMIF-Simulation-Guidance/ta-p/735201
Regards,
Adzim
New ContributorAdzim,
I did follow the guide you posted. I am concerned that the Channel Loss Calculation Tool is unable to handle signals that did not pass timing during the Hyperlynx DDRx Batch process, but we are told that we should not expect our simulation software to close timing.
How am I able to tell how bad the failed Hyperlynx timing is? Surely the DDR4 IP cannot close any arbitrary timing violation, so what is the actual usable range?
I can simply remove the failed signals from the simulation data and run the Channel Loss tool, but am I potentially making some wrong assumptions in doing so.
