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ConnorSousa's avatar
ConnorSousa
Icon for New Contributor rankNew Contributor
4 years ago

Arria 10 DDR4 IP - Using Hyperlynx DDRx Batch Wizard With Failed Simulation Results

Hello, Device: 10AX066K2F40E1HG We are designing a DDR4 LRDIMM interface for the above device using the EMIF IP. We have a board layout, and we are attempting to complete simulation to verify...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi ConnorSousa,


I'm sorry for the delay in providing reply to you.


I can suggest to you to refer to Arria 10 Design Guidelines document for more details on testing the board.

I'm not sure why you're getting the bad timing result which will be failed to test in the excel file.

I've asked for more details about the Channel Loss Tool from the engineering but they cannot done it yet because of limit bandwidth.

Please let me know if you found a better result when you doing the board simulation.


Thanks,

Adzim



Regards,

Adzim