Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why do I get corrupted packets at XGMII receive data path using 10GBASE-R PHY IP in Stratix® IV GT device?
Description You may get corrupted packets at XGMII receive data path using 10GBASE-R PHY IP in Stratix® IV GT device, due to a timing issue in the Quartus® II software version 10.0 and 10.0SP1. Resolution If you are using 10GBASE-R in Stratix IV GT device, we recommend that you install the Quartus II software version 10.0SP1, download and apply the following patch, and recompile your design to resolve this issue: Version 10.0sp1 patch 1.166 for Windows (.exe) Version 10.0sp1 patch 1.166 for Linux (.tar) Readme for the Quartus II software version 10.0sp1 patch 1.166 (.txt)Why does IP generation fail for some IP cores in Intel® Quartus® Prime Standard 19.1?
Description Due to missing Perl libraries in the Intel® Quartus® Prime Standard Edition software version 19.1, you may see various errors when generating some Platform Designer IP Cores. Error and Info messages indicating missing Perl library: Error: " Failed to find modelu Error: qsys-generate failed with exit code 1 Info: Can't locate Getopt/Long.pm Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition software version 19.1. Download and install Patch from the appropriate link below. Download patch Intel® Quartus® Prime Standard 19.1 Patch 0.01 for Windows (.exe) Download patch Intel® Quartus® Prime Standard 19.1 Patch 0.01 for Linux (.run) Download the Readme for Intel® Quartus® Prime Standard 19.1 Patch 0.01 (.txt)When reconfiguring a transceiver channel to switch between CMU PLL within the transceiver block to an additional CMU PLL or ATX PLL outside the transceiver block in Stratix IV GX device, why does the transceiver block create incorrect tx_clkout frequency
Description Intel has identified an issue in functional simulation and hardware for Stratix® IV devices when using Multi-PLL dynamic reconfiguration feature. This Multi-PLL feature enables you to reconfigure a transceiver channel to listen to additional transmitter PLLs located outside the transceiver block. When you use this feature in functional simulation you may observe that when you switch from a transmitter PLL within the transceiver block to a transmitter PLL (CMU/ATX) outside the transceiver block, the tx_clkout frequency is incorrect. In hardware, Quartus® II Software does not merge transmitter PLLs between multiple instances as expected. This issue is further explained with the following example: Consider a design with the following requirements One channel (A shown in the figure) running at OTU1 data rate (2.666 Gbps) One channel (B shown in the figure) capable of switching between OTU1, Fibre Channel 4G (4.25G), and SONET OC48 (2.488 Gbps) Assume that the above two channels need to placed in two different transceiver blocks. To implement this design, you must instantiate two ALTGX instances as shown below and use the Multi PLL reconfiguration feature (Option - "Use additional CMU/ATX PLL..." in the reconfiguration settings screen of the ALTGX Megawizard™) ALTGX Instance 1: has Channel A, Main PLL as PLL2 running at 2666 Mbps. ALTGX Instance 2: has Channel B, Main PLL as PLL0 (0 is the logical reference index of the PLL) running at 4250 Mbps, Additional PLLs as PLL1 running at 2488.32 Mbps and PLL2 running at 2666 Mbps In both the ALTGX instances, keep the same number of input reference clocks. This is required to share PLL2 between the two instances as described in step3 below. For this design configuration, only three PLLs are required to achieve this, as shown in Figure 1: Figure 1.Multi PLL Reconfiguration Example Design Scenario View full size Issue in functional simulation: In functional simulation when you switch from PLL0 to PLL2 using the 'Channel reconfiguration with TX PLL select' mode you will find that the tx_clkout frequency is incorrect. The following are the workarounds If CMU PLL is the 'outside transceiver block PLL' : - Perform TX PLL reconfiguration on the ‘outside transceiver block PLL’ ( PLL2) and THEN - Perform ‘Channel and TX PLL select’ on the desired channel (Channel B) to switch to this ‘outside transceiver block PLL’ If ATX PLL is the 'outside transceiver block PLL' : - Reconfiguration is not supported for ATX PLL. - Therefore make ATX PLL (PLL2) as your main PLL (default PLL that the channel listens to) and then - Switch to the CMU PLL (PLL0) within the transceiver block and back. Issue in hardware The QII software does not merge the PLL2 between the two instances which is incorrect. To merge the PLL2 of both the ALTGX instances into one physical transmitter PLL location,perform the following steps 1) Create a GXB TX PLL Reconfiguration group setting in the assignment editor and assign the same value (example: 0 or 1, 2,etc) for the tx_dataout of both instances 2) Manually assign location of the TX PLL that provides clocks to channels outside its transceiver block. In this example it is PLL2. The steps below show the manual location assignment method. Select the GXB Transmitter PLL from the Resource Section of the Fitter option in the Compilation Report. You can see the transmitter PLL node information for all the PLLs used in the design. For the PLL2, you can see two location assignments for the same node (example:tx_pll_edge0) Use one of the two locations for tx_pll_edge0 and manually assign it in the assignment editor as shown in Figure 2 Figure 2.Manual Assignment of Transmitter PLL View full size For information on the physical location of the PLL associated with the x, y coordinate, refer to AN578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices 3) Make the 'txplledge<x>.inclk<>' parameters identical in the ALTGX instances by modifying the wrapper file. For this example scenario, the Instance 2 wrapper file will show the following parameters tx_pll_edge0.inclk0_input_period = 9412, tx_pll_edge0.inclk1_input_period = 6430, tx_pll_edge0.inclk2_input_period = 6002, The Instance 1 wrapper file will show the following parameters tx_pll_edge0.inclk0_input_period = 0, tx_pll_edge0.inclk1_input_period = 0, tx_pll_edge0.inclk2_input_period = 6002, The QII software cannot merge PLL2 of both instances, when there is a mismatch between the input reference clock parameter (INCLK INPUT PERIOD) Therefore specify the tx_pll_edge<>. parameters from instance2 that has the maximum number of PLLs and include it in the wrapper for instance1. The following is the change required in instance1 tx_pll_edge0.inclk0_input_period = 9412, tx_pll_edge0.inclk1_input_period = 6430, tx_pll_edge0.inclk2_input_period = 6002, 3) Compile the design and observe the GXB Transmitter PLL from the Resource Section of the Fitter option in the Compilation Report You can now see that the transmitter PLLs from the two instances have been merged into a single physical location ( example:HSSIPLL_X119_Y10_N135)Why don't I see an difference in simulation results when I change the Tx drive strength settings of the IBIS-AMI transceiver models?
Description You will not see any difference in drive strength of Altera® Tx IBIS-AMI models if only the Ivod IBIS-AMI parameter is changed. You also need to change the appropriate selected analog IBIS-AMI model. The following document details how to change the Tx drive strength. IBIS-AMI Drive Strength Process (Right-click, Save as)Why jittery transmitter output is observed in 10G Base R PHY IP for Stratix IV GT?
Description Below is a transmitter output eye diagram example captured on the 10G Base R PHY IP transmitter output for ACDS 11.0 The transmitter slew rate was set incorrectly in ACDS 11.0 and above. The figure below shows the improved eye diagram after applying the recommended workaround or software patch. This issue is targeted to be fixed in ACDS 11.1. Resolution Here are the solutions for ACDS 11.0 and 11.0sp1: For ACDS 11.0: Below is the recommended workaround for ACDS 11.0. Please perform a backup before performing any modification to the Quartus® II library. Go to Altera® 10G Base R PHY IP root directory: For windows example: C:\altera\11.0\ip\altera\altera_10gbaser_phy\siv Change the following parameter in siv_10gbaser_pcs_pma_map.v in the PHY IP library folder: For windows example PHY IP library: C:\altera\11.0\ip\altera\altera_10gbaser_phy\siv\siv_10gbaser_pcs_pma_map.v In line 292, change the tx_slew_rate from “low” to “off” Re-generate the PHY IP megawizard™ and compile the design For ACDS 11.0SP1: Please download the appropriate Quartus II software version 11.0SP1 patch 1.07 from the following links: Quartus II software version 11.0SP1 patch 1.07 for Windows Quartus II software version 11.0SP1 patch 1.07 for Linux Quartus II software version 11.0SP1 ReadMe for patch 1.07 Caution: You must either have previously installed the Quartus II 11.0SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly. After you install the patch or workaround, please regenerate your 10G Base R PHY IP MegaCore® before you compile your design. Please take note the signal quality shown in the figure above may vary due to different transceiver\'s analog settings or PCB design.Is there a problem with dynamic reconfiguration for a receiver only channel in Stratix IV GX/GT devices?
Description Yes there is a problem with dynamic reconfiguration for a receiver only channel in Stratix IV GX/GT devices. For a receiver only channel, 25 words are read from the MIF instead of 38. To fix this problem, download and install the appropriate patch below. Download the Quartus II software version 11.0 SP1 Patch 1.06 for Windows (.exe) Download the Quartus II software version 11.0 SP1 Patch 1.06 for Linux (.tar) Download the Readme for the Quartus II software version 11.0 SP1 Patch 1.06 (.txt) You will then need to regenerate all the Receiver (ALTGX) megafunction instantiations and recompile the design so the MIF file is updated. This problem will be fixed in a future version of the Quartus II software.Error (21216): Cannot enable error detection cyclic redundancy check without instantiating the ALTERA_CRCERROR_VERIFY megafunction.
Description The EDCRC false error known issue found in Stratix® IV device and Arria® II device families require instantiation of an Altera CRCERROR Verify v12.0 megafunction. However, the Altera CRCERROR Verify v12.0 megafunction is not available in the Quartus® II software version 12.0. During compilation of a design that uses the error detection CRC feature, the Quartus II software reports above error. Resolution Refer to the Stratix IV device and Arria II device families errata sheet for the details on this EDCRC false error known issue. If you require the Altera CRCERROR Verify v12.0 megafunction for the EDCRC false error solution in the Quartus II software version 12.0, install patch 0.04 from the following links: Download the Quartus II software version 12.0 Patch 0.04 for Windows (.exe) Download the Quartus II software version 12.0 Patch 0.04 for Linux (.tar) Readme for the Quartus II software version 12.0 Patch 0.04 for Linux (.txt) This issue is scheduled to be fixed in a future version of the Quartus II software. Related Articles Error (21217): ALTERA_CRCERROR_VERIFY megafunction is not instantiated for stratixiv_crcblock primitive instance crcblock_componentHow do I resolve the "Can't recognize silicon ID for Device 1" error when programming the EPCS device using the EP4SGX180 enhanced Serial Flash Loader image?
Description You might see this error when programming an EPCS device using a .jic, .jam, or .svf file for designs targeting EP4SGX180 devices when using the Intel® Quartus® II Programmer version 9.1 SP2. The Intel Quartus II software contains an incorrect factory default enhanced Serial Flash Loader (SFL) image for the EP4SGX180 device. Resolution A patch is available to fix this problem for the Intel Quartus II software version 9.1 SP2. Download and install patch 2.52 from the following links: For Windows: Quartus II software version 9.1SP2 Patch 2.52 for Windows (.exe) Readme for the Quartus II software version 9.1 SP2 Patch 2.52 for Windows (.txt) For Linux: Quartus II software version 9.1 SP2 Patch 2.52 for Linux (.tar) Readme for the Quartus II software version 9.1 SP2 Patch 2.52 for Linux (.txt) This problem is scheduled to be fixed in a future release of the Intel Quartus II software. Related Articles Why can't I find SFL images for my device in the Quartus II software version 9.1 SP2?
