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Internal Error: Sub-system: RDB, File: /quartus/db/rdb/rdb_utility.cpp, Line: 1944 rval == nullptr
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see this internal error when performing an IP Upgrade. Resolution To work around this problem, delete the qdb folder before compiling the project. This problem is scheduled to be fixed in a future version of the Quartus® Prime Pro Edition Software.Why do I see generation error message when generating F-Tile Multi Channel DMA IP for PCI Express* Example Design using Quartus® Prime Pro Edition software version 24.1 for Windows*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and onwards for Windows, you may see the below error message when generating F-Tile Multi Channel DMA IP for PCI Express* Example Design. "file delete -force -- "${ORI_TEMP_PATH}/pcie_ed_rp/pcie.qsf"" (procedure "::intel_pcie_ftile_mcdma::generate_design_example_files" line 230) invoked from within "::intel_pcie_ftile_mcdma::generate_design_example_files ${QSYSTemPath} ${QSYSTemName} $TEMPPATH" (procedure "::intel_pcie_ftile_mcdma::generate_dynamic_qsys" line 1819) invoked from within "::intel_pcie_ftile_mcdma::generate_dynamic_qsys" (procedure "::intel_pcie_ftile_mcdma::dynamic_example_design" line 10) invoked from within "::intel_pcie_ftile_mcdma::dynamic_example_design" (procedure "::intel_pcie_ftile_mcdma::fileset::callback_example_design" line 2) invoked from within "::intel_pcie_ftile_mcdma::fileset::callback_example_design intel_pcie_ftile_mcdma_0_example_design" Error: Failed to generate example design example_design to: C:\altera_pro\24.1\quartus\bin64\intel_pcie_ftile_mcdma_0_example_design Resolution To resolve this problem, use one of the following methods: Perform the design example generation step in a Linux* environment. Use Quartus Prime Pro Edition software version 25.3. During the design example generation, disable the “Simulation” option in the IP GUI. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the Design Closure Summary fail in the Agilex® 7 FPGA HDMI IP Example Designs after changing the Layout Options under the IP GUI ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may observe the Design Closure Summary including Timing Closure marked as Fail in the Agilex® 7 FPGA F-Tile HDMI IP Design Example. Additionally, you may notice that the pll_frl_rx_outclk0 frequency is flagged as extremely high. This problem occurs when you change the “Layout Options” from its default values into any other value in the IP GUI. Resolution To work around this problem, follow the steps below: 1. go to "project" tab at Quartus -> Clean Project 2. locate directory rtl/ip/nios/nios_intel_hdmi_rx_phy/intel_hdmi_rx_phy_103/synth/nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v The filename nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v may vary for each generated design. Please verify files that start with nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103 (for example: nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxx.v). 3. Change the line #153 from [TMDS_1_GREEN_TRANSCEIVER_21] into [0] 4. Click saves and re-run the full compilation. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.3Views0likesWhy does the Design Closure Summary fail in the Agilex® 7 FPGA HDMI IP Example Designs after changing the Layout Options under the IP GUI ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, you may observe the Design Closure Summary including Timing Closure marked as Fail in the Agilex® 7 FPGA F-Tile HDMI IP Design Example. Additionally, you may notice that the pll_frl_rx_outclk0 frequency is flagged as extremely high. This problem occurs when you change the “Layout Options” from its default values into any other value in the IP GUI. Resolution To work around this problem, follow the steps below: 1. go to "project" tab at Quartus -> Clean Project 2. locate directory rtl/ip/nios/nios_intel_hdmi_rx_phy/intel_hdmi_rx_phy_103/synth/nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v The filename nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxxxxx.v may vary for each generated design. Please verify files that start with nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103 (for example: nios_intel_hdmi_rx_phy_intel_hdmi_rx_phy_103_xxxx.v). 3. Change the line #153 from [TMDS_1_GREEN_TRANSCEIVER_21] into [0] 4. Click saves and re-run the full compilation. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the TX Throughput value shown in Ethernet Toolkit for the F‑Tile Ethernet FPGA Hard IP Design Example not match the expected data rate?
Description In F‑Tile Ethernet FPGA Hard IP Design Example generated using Quartus® Prime Pro Edition software versions 25.3.1 and earlier, you may notice that the TX Throughput reported by the Ethernet Toolkit appears lower than the expected line rate. This behavior is expected. The ROM‑based packet generator included in the design example has the following characteristics: It defaults to a 64‑byte packet size, and It inserts non‑zero inter‑packet gaps (IPG) These factors inherently reduce the measured throughput compared to the theoretical maximum line rate. Resolution To accurately validate the TX Throughput of the design, Altera recommends to use a standard Ethernet traffic tester capable of running in client loopback mode. This allows to measure the actual TX throughput without limitations imposed by the built‑in ROM packet generator. There is no plan to fix this problem.Why is no video output displayed when migrating the F-Tile SDI II FPGA IP Design Example with 12G multi-rate from an older version to Quartus® Prime Pro Edition Software version 25.3.1 patch 1.10 ?
Description Due to an issue in the Quartus® Prime Pro Edition Software Programmer version 25.3.1, users may observe that no SDI II video output is displayed on the receiver side when using the F-tile SDI II FPGA IP Design Example with 12G multi-rate on Agilex® 7 FPGA devices. This issue is caused by forcing lock-to-data. For SDI dynamic reconfiguration designs, manual CDR lock mode with lock-to-ref enabled should be used. Resolution To solve this problem, use below method 1. Open Platform Designer of sdi_rx_sys.qsys 2. Disable fgt_rx_set_locktodata port, Enable fgt_rx_set_locktoref port 3. At System View Should not seeing fgt_rx_set_locktodata port Export fgt_rx_set_locktoref port out 4. Sync info and regenerate HDL 5. Open rx_top.sv file Comment out / remove fgt_rx_set_locktodata Add exported fgt_rx_set_locktoref port and connect to ~rx_set_ltd 6. Save and recompile design This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why is the maximum number of I/O PLLs incorrectly reported in the Total PLLs Fitter Summary report?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the maximum number of I/O PLLs for Agilex® 5 FPGA devices is stated incorrectly in the Total PLLs Fitter Summary report. Resolution The compilation will pass as long as the number of I/O PLLs used in the design does not exceed the actual maximum number of I/O PLLs supported by the specific device. The correct maximum number of I/O PLLs supported can be checked from the PDF with the title of Agilex 5 FPGAs and SoCs <Series> Product Table. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why the Agilex® 5 FPGA Hard Processor System CoreSight Trace is not working?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, when enabling the Agilex® 5 FPGA Hard Processor System Coresight Trace it is not functioning. Resolution To work around this problem, enable either one of the fabric debug feature such as APB or JTAG and tie off the signals if they are not used. This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does preforming read and write data via FPGA to HPS bridge fail when SMMU is enabled in HPS IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 release and earlier, the Agilex™ 5 HPS FPGA to HPS bridge could not be accessed by the FPGA Fabric when SMMU is enabled. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v24.3.1.Error: error deleting "<path>/0001_intel_pcie_ftile_mcdma_0_gen//pcie_ed_rp/pcie.qsf": permission denied
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier on a windows* 11 system, you may see the below error during generating example designs for F-tile PCIe Multichannel DMA IP for PCI Express IP. Error: error deleting "<user default temporary folder>/alt0446_17235589168751817424.dir/0001_intel_pcie_ftile_mcdma_0_gen//pcie_ed_rp/pcie.qsf": permission denied Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.