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Why is the maximum number of I/O PLLs incorrectly reported in the Total PLLs Fitter Summary report?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the maximum number of I/O PLLs for Agilex® 5 FPGA devices is stated incorrectly in the Total PLLs Fitter Summary report. Resolution The compilation will pass as long as the number of I/O PLLs used in the design does not exceed the actual maximum number of I/O PLLs supported by the specific device. The correct maximum number of I/O PLLs supported can be checked from the PDF with the title of Agilex 5 FPGAs and SoCs <Series> Product Table. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why the Agilex® 5 FPGA Hard Processor System CoreSight Trace is not working?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, when enabling the Agilex® 5 FPGA Hard Processor System Coresight Trace it is not functioning. Resolution To work around this problem, enable either one of the fabric debug feature such as APB or JTAG and tie off the signals if they are not used. This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does preforming read and write data via FPGA to HPS bridge fail when SMMU is enabled in HPS IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 release and earlier, the Agilex™ 5 HPS FPGA to HPS bridge could not be accessed by the FPGA Fabric when SMMU is enabled. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v24.3.1.Error: error deleting "<path>/0001_intel_pcie_ftile_mcdma_0_gen//pcie_ed_rp/pcie.qsf": permission denied
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier on a windows* 11 system, you may see the below error during generating example designs for F-tile PCIe Multichannel DMA IP for PCI Express IP. Error: error deleting "<user default temporary folder>/alt0446_17235589168751817424.dir/0001_intel_pcie_ftile_mcdma_0_gen//pcie_ed_rp/pcie.qsf": permission denied Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do we observe small increase in the duration of o_rx_pfc port assertion during the “PAUSE” state in the designs generated using F-Tile Ethernet Hard IP for F-Tile devices when cycles with incoming frames are padded?
Description An Ethernet design generated using F-Tile Ethernet hard IP in Quartus® Prime Pro Edition Software for F-Tile devices is showing small increase in the duration of o_rx_pfc port assertion for cycles with incoming padded frames. The slight increase in the duration of o_rx_pfc port assertion during the “PAUSE” state is due to the cycles carrying the padded data not contributing to the PAUSE time. For data rates ranging from 10G-200G, we observe an increase in the duration of 15ns for 10G and 2.5ns for 200G for each padded frame received during “PAUSE” state. 400G PFC implementation differs from other line rates so there won’t be any increase in duration of o_rx_pfc port assertion. Resolution There is no workaround and no plan to fix this problem.Why does fitter take a long time when a large number of protocol IP instances/profiles are used for GTS Dynamic Reconfiguration in the Quartus® Prime Pro Edition software versions 25.3.1 and earlier?
Description The fitter process may take significantly longer when many IP instances or profiles are used for Dynamic Reconfiguration in Quartus Prime Pro Edition software versions 25.3.1 and earlier. Depending on the number of IP profiles, the fitter may take several days to complete. Resolution The fitter process may take significantly longer when many IP instances or profiles are used for Dynamic Reconfiguration in Quartus Prime Pro Edition software version 25.3.1 and earlier. To overcome this problem, some of the precautions measured users will have to take to prevent this longer fitter runtime problem. Some steps are mentioned in section 7 point#6 of GTS Dynamic Reconfiguration Controller IP User Guide, version 25.3.1. Add SDC constraints for mutually exclusive IP variants into clock groups, although this is ultimately required. Identifying and constraining these exclusive clocks constraints before running the fitter can help avoid prolonged fitter runtimes. For example: set_clock_groups -physically_exclusive -group [get_clocks dr_top_inst|ip_variant_1_inst*|*] -group [get_clocks dr_top_inst|ip_variant_2_inst*|*] Add the following constraints in SDC can help avoid prolonged STA runtime for a large number of profiles. qsta_utility::disable_slower_multi_clocks Additional include the following line in the Dynamic Reconfiguration Quartus Project QSF file can significantly reduce fitter time for a large number of profiles. set_global_assignment name REMOVE_SLOWER_CLOCKS_DURING_FITTER ON Note: In your project .qsf file, ensure that the SDC_FILE QSF assignment is placed after the IP_FILE QSF assignments. Failure to do so results in a warning in the Quartus Prime Pro Edition software, and the SDC constraints are then ignored as mentioned in Article 343689. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the fitter fail when a large number of protocol IP instances/profiles are used for GTS Dynamic Reconfiguration in the Quartus® Prime Pro Edition software versions 25.3.1 and earlier?
Description When using a large number of IP instances for GTS Dynamic Reconfiguration, a fitter failure may occur if the combined total of channels and any IP GTS PMA/FEC Direct IP instances or GTS CPRIPHY IP Instances exceeds 71 for Dynamic Reconfiguration in Quartus® Prime Pro Edition software versions 25.3.1 and earlier. This limitation is explicitly stated in section 5.1 of the GTS Dynamic Reconfiguration Controller IP User Guide version 25.3.1. Resolution There is no workaround available in Quartus Prime Pro Edition software versions 25.3 and earlier, but patch is available for Quartus Prime Pro Edition software version 25.3.1 Patch 1.15 corresponds to this problem. You can download and install version 25.3.1 patch 1.15 below. To prevent this problem, ensure that the maximum limit of 71 instances is not exceeded in your dynamic reconfiguration design, as specified in section 5.1 of the GTS Dynamic Reconfiguration Controller IP User Guide version 25.3.1. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the SD/eMMC U-Boot driver fail to select the SDR12 mode for Agilex® 5 FPGA and Agilex® 3 FPGA devices in release 25.3.1 release and before?
Description Due to a problem in the U-Boot SD/eMMC driver in Agilex® 5 FPGA and Agilex® 3 FPGA devices in release 25.3.1 and before, U-Boot fails to select the SD SDR12 mode regardless of using the sd-uhs-sdr12 parameter in the device tree. The reason behind this problem is that the driver tries the SD_HS (50 MHz) mode first, so if this succeeds, then the SDR12 (25 MHz) is not tried. Because of this problem, currently, there is no direct method to force the driver to choose SDR12 mode. Resolution To workaround this problem, you need to use the following configuration in the device tree along with the SD/eMMC driver source code modification: 1. U-Boot device tree configuration: Remove no-1-8-v: Allows the MMC stack to perform voltage switching to 1.8V, which is required for UHS modes Remove cap-sd-highspeed: Ensures SDR12 becomes the highest priority mode available Add sd-uhs-sdr12: Explicitly declares SDR12 support &mmc { status = "okay"; no-mmc; disable-wp; //no-1-8-v; // Remove or keep commented out //cap-sd-highspeed; // Remove or keep commented out sd-uhs-sdr12; // Add this property vmmc-supply = <&sd_emmc_power>; vqmmc-supply = <&sd_io_1v8_reg>; max-frequency = <200000000>; sdhci-caps = <0x00000000 0x0000c800>; sdhci-caps-mask = <0x00002007 0x0000ff00>; // ... (rest of PHY timing configuration remains unchanged) }; 2. Modify the U-Boot drivers/mmc/sdhci-cadence.c source code as follows: You must update the host->quirks parameter to disable the SD High Speed mode at the driver level, providing an additional safeguard to ensure SDR12 is selected. static int sdhci_cdns_probe(struct udevice *dev) { : host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; // Add this line : } This problem will be fixed in a future release.Why isn't the F-Tile Serial Lite IV Toolkit shown in the System Console window when using the Quartus® Prime Pro Edition software version 25.3 and 25.3.1 ?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and 25.3.1, the F-Tile Serial Lite IV Toolkit is not shown in the System Console window. Resolution A patch is available to fix this problem for the Quartus Prime Pro Edition software versions 25.3.1. Download and install patch 1.11 below. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why can't I connect two LVDS SERDES instances to one external PLL in Agilex™ 5 device?
Description When trying to implement the structure as shown in “Figure 40. I/O PLL Driving Mixed Receiver and Transmitter Channels in the Same Sub-Bank” of LVDS SERDES User Guide Agilex™ 5 FPGAs and SoCs with two separate LVDS SERDES IP instances and one external IOPLL IP instance, you will see the following fitter error similar to the followings: Error(14996): The Fitter failed to find a legal placement for all periphery components Error(14986): After placing as many components as possible, the following errors remain: Error(175001): The Fitter cannot place 1 CLKGEN, which is within LVDS SERDES IP lvds_serdes_tx_extpll_intel_lvds_2400_mqdyxqy. Error(16234): No legal location could be found out of 7 considered location(s). Reasons why each location could not be used are summarized below: Error(23276): Could not find usable path between source IOPLL: O_LOCK[0] and the CLKGEN: I_PLL_LOCK[0] Resolution For Agilex™ 5, the following rules restrict the LVDS SERDES IP instances placement described above: Each LVDS SERDES IP instance in the mode of TX, RX Non-DPA or RX DPA-FIFO uses one CLKGEN atom. One PLL can only fanout to one CLKGEN atom. Therefore, you cannot connect a single IOPLL to two LVDS IP instances if both of them are in the mode of TX, RX Non-DPA or RX DPA-FIFO. If TX and RX (DPA FIFO or Non-DPA) are sharing the same IOPLL, TX and RX must be generated from a single LVDS IP instance.