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Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master
Hi all, I've put together a tutorial on how to use the Altera JTAG-to-Avalon-MM master and Altera Verification IP Avalon-MM BFM Master under both SOPC builder and Qsys. http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip) The tutorial walks the user through the creation of an SOPC or Qsys system design, and provides scripts that automate the re-generation of the system. The tutorial shows how to simulate using Modelsim-ASE, and shows how to communicate with the hardware using System Console, quartus_stp, and then how to run a TCP/IP server under System Console or quartus_stp, and then communicate with that server from client code written in Tcl/Tk (a simple GUI) and a command-line C interface. Let me know if you like it, or have feedback/suggestions on how to improve the document. Cheers, Dave
ERROR: (vlog-7) Failed to open, trying to run Intel example project in ModelSim
Tool = Quartus Pro 2019.1, ModelSim 10.6d (subscription edition) FPGA Component = Stratix 10 (1SX280LU2F50E2VG) I am running into a problem with the simulation of example design for the Low Latency Ethernet 10G MAC IP. I created an IP component using an example design preset for the IP as below. I then generate the example design for this IP. 10M/100M/1G/2.5G/5G/10G USXGMII Ethernet with 1588 Example Design (Stratix 10) I open ModelSim and change directory to <example_path>/simulation/ed_sim/mentor. Then I type "source tb_run.tcl" in the transcript window. Intel User Guide 20073 explains this process (section 1.3). The script begins running for a while and then I get the following error. ** Error: (vlog-7) Failed to open design unit file "../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_eth_1588_tod_10g/altera_merlin_slave_translator_191/sim/address_decoder_channel_eth_1588_tod_10g_altera_merlin_slave_translator_191_x56fcki.sv" in read mode. I've searched online for solutions and found some. I've tried the following: Windows path depth too long - I reduced the path length but still get error. One post suggested rebooting - I rebooted but still get the error. A post suggested checking that file exists - I verified the .sv file in the error message is present and not read only. Anyone have any other suggestions? I tried two other presets in the IP and they all fail at exactly the same point and exactly the same SV file.
Agilex® 7 P-Tile Multi-Channel DMA Debug Toolkit isn't working in Quartus® v22.4
This is an issue sharing of Agilex P-tile MCDMA PCIe Debug Toolkit : Agilex® 7 P-tile Multi Channel DMA Intel® FPGA IP for PCI Express Debug Toolkit isn't working for Gen4 1x8 in Quartus® v22.4. However the P-Tile MCDMA DTK is working fine in Gen4 1x16. Gen4 1x8: Not able to open Toolkit as it throws a timeout error. This problem is planned to be fixed in future release of Quartus® Pro software version. For more information about P-tile MCDMA PCIe IP, refer to the 'Multi Channel DMA Intel® FPGA IP for PCI Express User Guide' https://www.intel.com/content/www/us/en/docs/programmable/683821/23-1/before-you-begin.htmlaltera_dma driver for PCIe
Hi everyone, i'm using an Arria V starter kit for PCIe application and i used the reference design posted in altera wiki. The application software reported success in one PC but not in other with different features. The driver code is installed in two with success but in one, user application reported timeout for read, write and simultaneous RW. Had anyone has the same problem? Have anyone some suggestion about what can i do to try solve this problem?DisplayPort Only Connects to Windows not Linux
Hi, I am trying to use the DisplayPort sample design on a Stratix 10 board. I have implemented the exact sample project from Intel with the Bitec daughter card but am seeing some issues. When I plug a Windows PC (7 or 10) into the daughter card it immediately performs the link training and connects to the Operating System. Using SignalTap I can see data flowing out of the Clkrec core (VSYNC, HSYNC, DE, Data). When I plug in a monitor to the TX port I can see a windows desktop as if it were a second monitor to my Windows PC desktop. When I plug a linux machine (or same hardware but dual boot) into the DisplayPort RX port, Linux recognizes the DisplayPort sink as a monitor. However I am not seeing any data come out of the Bitec Clkrec. Linux is reporting that it found valid modes for the DisplayPort monitor. Can you help me figure out why the DisplayPort core has no trouble connecting to Windows but has trouble connecting to Linux? Setup: OS: CentOS 6 Graphics Card Vendor: NVIDIA DisplayPort Core: GPU mode enabled, AUX debug enabled, core is set for HBR3 and 4k60 resolution. Tool: Quartus 19.1 Thanks! Danielverilog- parameterized mux
For the life of me I cannot figure out how to generate a parameterized mux in verilog... I understand how to generate, say, a 4:1 MUX of "N" bits wide... But I am trying to generate an N:1 mux, of only 1 bit wide. I've been scouring the googleweb for weeks with no such luck (aside from hit after hit for a variable-width mux)... Have I stumbled upon something impossible? thanks, ..daneSystem console giving up when running the command "TEST_PHYSERIAL_LOOPBACK 0 1G 1000"
Hi, I have generated the design example for Low latency ethernet 10g mac intel fpga ip-- 10M/100M/1G/10G example design(Arria 10) by following the below document. https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/10m-100m-1g-10g-ethernet-design-example.html While testing it on the hardware, I am getting the below error from system console. “error: master_write_32: This transaction did not complete in 60 seconds. System console is giving up. While executing “master_write_32 sport_id $address $wdata” (procedure “reg_write” line 7) invoked from within “reg_write $PHY_IP_BASE_ADDR $seq_control 0X111” (procedure “SETPHY_SPEED_1G” line 😎 invoked from within “CONFIG_IPORT $speed_test” (procedure “TEST_PHYSERIAL_LOOPBACK” line 10) invoked from within TEST_PHYSERIAL_LOOPBACK 0 1G 1000” I have changed the USB blaster frequency to 16MHz,6MHz but still I am getting the issue. Details: Quartus used : Quartus prime 22.2 Board :Intel arria 10 GX development board Device : 10AX115S2F45I1SG. Below are the clock pin assignments Name pin assigned mm_clk 125Mhz BD24 clk_125 ref_clk_1g 125MHz N37 REFCLK_SMA (modified using clk controller). ref_clk_10g 644.53125Mhz AA37 REFCLK_SFP
FIFOed UART Qsys Generation Error with Qsys Standard v18.1
Hello, when generating a FIFOed UART with Qsys Standard v18.1 as provided here https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005RTHQA2&artTopicId=0TO0P000000MWKBWA4&action=view I receive the following Qsys generation errors: Info: tube_uart_0: Starting FIFOed UART Generation at C:/xy/Qsys/fifoed_uart … Info: tube_uart_0: Starting RTL generation for module 'f2flink_tube_uart_0' … Info: tube_uart_0: Info: tube_uart_0: ERROR: Info: tube_uart_0: no width for __0__/* synthesis keep */ Error: tube_uart_0: Failed to generate module f2flink_tube_uart_0 Info: tube_uart_0: Done RTL generation for module 'f2flink_tube_uart_0' Info: tube_uart_0: "f2flink" instantiated fifoed_avalon_uart "tube_uart_0" Error: Generation stopped, 15 or more modules remaining This issue seems to be related to the Tx FIFO option (see screenshot). Could you please let me know how this problem can be fixed and if a patch is available? Thank you. Best regards, Thomas