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SThom66's avatar
SThom66
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5 years ago

ERROR: (vlog-7) Failed to open, trying to run Intel example project in ModelSim

Tool = Quartus Pro 2019.1, ModelSim 10.6d (subscription edition) FPGA Component = Stratix 10 (1SX280LU2F50E2VG)

I am running into a problem with the simulation of example design for the Low Latency Ethernet 10G MAC IP. I created an IP component using an example design preset for the IP as below. I then generate the example design for this IP.

10M/100M/1G/2.5G/5G/10G USXGMII Ethernet with 1588 Example Design (Stratix 10)

I open ModelSim and change directory to <example_path>/simulation/ed_sim/mentor. Then I type "source tb_run.tcl" in the transcript window. Intel User Guide 20073 explains this process (section 1.3). The script begins running for a while and then I get the following error.

** Error: (vlog-7) Failed to open design unit file "../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_eth_1588_tod_10g/altera_merlin_slave_translator_191/sim/address_decoder_channel_eth_1588_tod_10g_altera_merlin_slave_translator_191_x56fcki.sv" in read mode.

I've searched online for solutions and found some. I've tried the following:

  1. Windows path depth too long - I reduced the path length but still get error.
  2. One post suggested rebooting - I rebooted but still get the error.
  3. A post suggested checking that file exists - I verified the .sv file in the error message is present and not read only.

Anyone have any other suggestions? I tried two other presets in the IP and they all fail at exactly the same point and exactly the same SV file.

7 Replies

    • Shubha46's avatar
      Shubha46
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      3 years ago

      Thank you for the answer. It was a great help.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    I am able to simulate the design example though. Not sure if this works, one suggestion is make sure that the path does not have any empty space in between. e.g. C:\project example -> C:\project_example.

    • SThom66's avatar
      SThom66
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      5 years ago

      Yes, I did also check that there are no spaces in the path. To be sure I did regenerate the example project this morning and placed it directly on C:/ as shown.

      C:\EXAMPLE_DESIGN\LL10G_10G_USXGMII_1588v2\simulation\ed_sim\mentor

      I still get the error. Always the same file.

      ** Error: (vlog-7) Failed to open design unit file "../../../rtl/address_decoder/ip/address_decoder_channel/address_decoder_channel_eth_1588_tod_10g/altera_merlin_slave_translator_191/sim/address_decoder_channel_eth_1588_tod_10g_altera_merlin_slave_translator_191_x56fcki.sv" in read mode.

      I also tried generating it in the latest version of Quartus (20.2 Pro) and still get the same error. I am running Windows 10. You running the same? Do you have "LongPathsEnabled" in the Windows registry?

      You followed the same steps?

      1) generate the example project

      2) start ModelSim

      3) change directory to C:\EXAMPLE_DESIGN\LL10G_10G_USXGMII_1588v2\simulation\ed_sim\mentor

      4) type source tb_run.tcl

      Thanks.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    I test again in Window 10 and I able to duplicate the error. Last time I tested it on RHEL successfully.

    Do you have it in Window 10?


    • SThom66's avatar
      SThom66
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      5 years ago

      Hi ShayanYewT_Intel, Yes I am using Windows 10.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi,

    We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

    Best Regards,

    Shyan Yew