Recent Discussions
Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation
I have followed the recipy as described in "ug_a10_pcie_avst.pdf" , "Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express* User Guide", and the configuration seems to have downloaded correctly. However, when I try to simulate in Modelsim, as described in par. 2.4 "simulating the design", by typing "do msim_setup.tcl" (works fine), then "ld_debug", a lot compiles, until the last succesful compile of # Top level modules: # DUT_pcie_tb_ip # End time: 14:29:58 on Jun 26,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017 # Start time: 14:29:58 on Jun 26,2020 Then the following error appears: # vlog -reportprogress 300 -sv ../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_180/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_180_zc3dnuy.sv -L altera_common_sv_packages -work altera_conduit_bfm_180 # ** Error: (vlog-7) Failed to open design unit file "../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_180/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_180_zc3dnuy.sv" in read mode. # No such file or directory. (errno = ENOENT) # End time: 14:29:58 on Jun 26,2020, Elapsed time: 0:00:00 See also line 6119 in the attached transcript file This module "pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_180_zc3dnuy.sv" does not exist in the directory, however, there is a pcie_example_design_inst_board_pins_bfm_ip.csv file in which reference is made to this module. Please advice. Regards, Pieter
Agilex-7 AXI MCDMA for PCIe hang
Hi! I'm working with AGIB023R18A1E1VC device and having issues with AXI Multichanned DMA IP for PCIe. Since I require a PCIe bridge, I configured the IP in MCDMA+BAS+BAM mode (PCIe Gen 4, 512-bit), generated an example design, and integrated the subsystem into my project. Although I do not use MCDMA, I rely heavily on the BAS and BAM functionality. The issue I’m seeing is that writing more than 448 bytes to the BAS causes the host to hang and subsequently reset. Notably, between the write transaction and the host reset, the FPGA internal logic is still able to write to the BAS, indicating no hang on the AXI bus. There are no issues with read transactions. We observe this issue not with only one card. At first we run into it in Q25.1 but still have it in Q25.3.1 If you need some captures from the signal tap or any additional details I may provide them. Thank you in advance! Mikhail.
Can't generate F-Tile Ethernet Hard IP Design Example
When I try to generate an example design for the F-Tile Ethernet Hard IP or even the F-Tile Low Latency 100G Ethernet IP, the generating step gets stuck in a loop and will stay that way until I manually stop it in Task Manager. Has anyone else encountered this issue?
Constraints not being picked for DCFIFO
Hi, I am having various DCFIFOs in my design. I have applied constraints according to the ug_fifo. Attaching link for the reference https://faculty-web.msoe.edu/johnsontimoj/EE3921/files3921/ug_fifo.pdf In the DRC report, I am getting a violation of CDC-50007 which shows CDC bus with insufficient constraints and it is showing set_max_skew and set_data_delay are violated. This issue is not coming up for all the DCFIFOs in the design. The violations are there in the path of the delayed_wrptr_g[*] to rs_dgwp|dffpipe*|dffe and rdptr[*] to ws_dgrp[*] |dffpipe*|dffe. In the same DCFIFO, violation is coming only on either wr_ptr or rd_ptr. Could you suggest why this constraint is not being picked in some selected FIFOs and only in either wr / rd paths? set_data_delay is not prescribed as per the ug_fifo.
Connecting Intel Agilex FPGA to DE1-SoC via Hub
Hello, I have an Intel Agilex FPGA with QSFP-DD 10 GbE PHY, a DE1-SoC board with 1 GbE PHY, and an Ethernet Hub 1 GbE. I want to connect the Agilex to the DE1-SoC through this hub. I understand the DE1-SoC only supports 1 GbE while the Agilex PHY is capable of 10 GbE. I would like to know the best way to communicate between these boards. Is it possible to configure the Agilex Ethernet IP and PHY to 1 GbE so it can communicate directly through the hub without a physical adapter? If not, would a media converter or adapter be needed to downspeed from 10 GbE to 1 GbE? Are there any recommended best practices for connecting an Agilex to a slower device like the DE1-SoC via Ethernet? Any guidance or experience would be greatly appreciated. Thank you!