Recent Discussions
Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3)
Hello, I posted this question before on the Quartus Prime Forum but saw this forum and thought maybe this would be a better place to post it. Sorry if this is considered spam and not allowed: I want to integrate the Avalon Streaming Single Clock FIFO IP (AVST FIFO IP) with the GTS Ethernet Hard IP (GTS EHIP) , but the GTS EHIP outputs signals rxstatus_valid and rxstatus_data, that don't interface with the AVST FIFO IP. The AVST FIFO IP is in a custom module that sits in between the GTS EHIP and the rest of the 1x10G Ethernet System Example Design: Agilex 5 FPGA E-Series Modular Development Kit (Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). How should I handle these signals? Can I ignore them? Is there a example reference design that does this? Thank you for the help! IP Blocks (left:EHIP, right:avst sc fifo ip): SC FIFO Parameters:
25G Ethernet IP for Stratix10
Team, We have 25G Ethernet IP for stratix10 which suport 10G and 25G dynamically. How to set it to 10G rate and 25G as and when required. We understating it is done by writing to some registers through the reconfiguration interface. We cannot find these registers and the process to be followed to switch the 10G25G interface rates. Regards amol
Error when simulating F-tile Ethernet example design
When running "run_vcsmx.sh" following set of errors occurs Just one example Error-[URMI] Unresolved modules ../ex_200G/sim/../../hardware_test_design/support_logic/eth_f_hw_auto_tiles.sv, 2655 "intfc_m_hdpldadapt_avmm1_mux #(.topology("UX16E400GPTP_XX_DISABLED_XX_DISABLED"), .maib_id(0), .num_ip_on_intfc_00(2), .system_pll_ip_index_on_intfc_00(1), .num_ip_on_intfc_01(2), .system_pll_ip_index_on_intfc_01(1)) z1577b_x0_y0_n0__avmm1_0( .pld_avmm1_busy_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_busy_real), .pld_avmm1_clk_rowclk_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_clk_rowclk_real), .pld_avmm1_cmdfifo_wr_full_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_cmdfifo_wr_full_real), .pld_avmm1_cmdfifo_wr_pfull_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_cmdfifo_wr_pfull_real), .pld_avmm1_read_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_read_real), .pld_avmm1_readdata_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_readdata_real), .pld_avmm1_readdatavalid_rea ... " Module definition of above instance is not found in the design. eth_f_hw_auto_tiles.sv is a 36 MB sv-file, making debugging of this quite tedious. I've only followed the design example user guide which states the script should be able to run out of the box.
SerialLite II license for Arria10 FPGA
I purchased a SerialLite II license and received the license file. However, I need a special license to support Arria 10 FPGAs. In previous years, I obtained this license by contacting Altera technical support through a sales representative. This year, I was advised to contact Altera through the forum. Please help me find the correct way to obtain the necessary license file.
AI Suite Docker Update?
Hello Community, I see the 2026.1.1 version of the AI Suite is available - https://www.altera.com/downloads/add-development-tools/fpga-ai-suite-version-2026-1-1 Is there an expected delay or expected date for the Docker to reflect this version? - https://hub.docker.com/r/alterafpga/fpgaaisuite Thank you,Agilex7 F-TILE ethernet hard IP 200G
Now we develop a project with agilex7 fpga. In the project we generate 200Gx4 ethernet hard ip. during testing on-board, the reset flow of the ethernet IP failed to complete successfully: The IP output signals o_rst_ack_n / o_tx_rst_ack_n / o_rx_rst_ack_n remain permanently High and never pull Low. This causes the input reset signals i_rst_n / i_tx_rst_n / i_rx_rst_n fed into the Ethernet IP to stay stuck in the Low-level reset state and never exit reset. the following signal status as follow by read register: tx_lanes_stable = 0 sys_pll_locked = 0 tx_pll_locked = 1 the IP reset sequence in the IP datasheet shows: so what should we do for the next step? Do you have any suggestion?
Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted
Where can I find any public available dev kit design example for the Agilex3 or Agilex which can implement the GTS Eth HIP as generated by Quartus Pro v25.3 and successfully build a sof file? A set of pin locations and IO standard settings for the AXE5 Eagle would be optimal, but any other dev kit would be helpful. According to the "GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs" (848477) page 29 under "Target Development Kit Tab" is says: "Target development kit option specifies the target development kit used to generate the project. Ensure the pin assignments in the .qsf file are appropriate." But it seems like this will only set the BOARD parameter in the resulting qsf, e.g. when using the Premium Development Kit it results in the following addtion to the qsf file: set_global_assignment -name BOARD "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1" which results in no location or IO standard settings in the qsf and I/O Assignment Warnings in the fitter report after the build: +-----------------------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; o_tx_serial_data[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; o_tx_serial_data_n[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_lowpwr ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_rstn ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; i_reconfig_clk ; Missing I/O standard ; ; i_rx_serial_data_n[0] ; Missing I/O standard ; ; i_rx_serial_data[0] ; Missing I/O standard ; ; i_clk_ref_p ; Missing I/O standard ; ; o_tx_serial_data[0] ; Missing location assignment ; ; o_tx_serial_data_n[0] ; Missing location assignment ; ; qsfp_lowpwr ; Missing location assignment ; ; qsfp_rstn ; Missing location assignment ; ; i_reconfig_clk ; Missing location assignment ; ; i_rx_serial_data_n[0] ; Missing location assignment ; ; i_rx_serial_data[0] ; Missing location assignment ; ; i_clk_ref_p ; Missing location assignment ; ; i_refclk2pll_p ; Missing location assignment ; +-----------------------+-----------------------------------------------------------------------------------------------+ Whenever I try to assign these myself I get errors like Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IPFLUXTOP_UXTOP_WRAP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 IPFLUXTOP_UXTOP_WRAP, which is within GTS Ethernet Hard IP ex_10G_intel_eth_gts_1000_6dyx4dq. or this or other type of layout or clocking type constraint errors: Error (11216): Output port "O_SYSPLL_C0" of "SM_HSSI_PLL_WRAP" cannot connect to PLD port "CLK" of "FF" for node "kr_dut|intel_eth_anlt_gts_0|ip_inst|sip_inst|u_intel_eth_anlt_gts_csr_top|u__intel_eth_anlt_gts_csr_avmm_arb|o_avmm_rdata[0]". It would be nice if I could obtain a set of correct and working pin assignment which actually results in a working sof file so I can try to understand what the actual constraints are. Is there a dev kit as described which the pin assignments are generated or provided or could anybody please provide a set of pin assignments for the above signals for a dev kit? Cheers!