Using registers to debug in SignalTap

I've been using this technique for several months, and I'm curious if anyone else does the same or if there is a better way.

When I want to track a signal in SignalTap, I do the following:

1. Add a RegOut block to my model and give it a name like "DebugFIFODataOut".

2. Generate DSP Builder, Qsys, and run Synthesis

3. In SignalTap, search for *debugfifodataout* with filter set to Design Entry (all names).

4. Drill down to the busSlaveFabric_*

5. Insert the in_AMMregisterPortData* and in_AMMregisterPortWriteEn*

6. Add meaningful Aliases to the signals

Note that you can use the write signal on the register as well as you are not actually concerned with register itself.