quartus pro 25.3 bug?
Now I am developing a project with agilex7 base on the quartus pro 25.3. the project contains R-TILE pcie hard ip and F-tile ethernet hard ip. During board bring-up debugging, we frequently encounter non-deterministic discrepancies between actual hardware behavior and simulation results. For instance, on a certain platform, the PCIe device fails to be enumerated by the host. Probing the Avalon-ST TX interface of the PCIe hard IP reveals continuous toggling on both the hvld and dvalid signals. However, we have verified that no traffic is being sourced to this interface, meaning these two signals should theoretically remain idle without constant toggling. And the timing of the project is cleaning. How should we proceed to troubleshoot this issue? Should we try upgrading the Quartus version as a potential solution?
DDR2 license Question
The customer obtained the DDR2 license through the Altera website. Does this IP license have any time limitation or other usage restrictions? When generating the project for the EP4CE75U19I7N device, Quartus only generates project.sof and does not generate project_time_limited.sof.How does the FPGA AI Suite utilize Agilex 5 DSP Blocks?
Hello Altera Community. I have a module called "dot_bf16" that uses the bf16 floating point format to calculate dot product and I am wondering if it uses the Agilex5 AI optimized DSP blocks to do this. I can't myself see how the DSP blocks are configured because they are all encrypted. 1. Agilex™ 5 Variable Precision DSP Blocks Overview • Variable Precision DSP Blocks User Guide Agilex™ 5 FPGAs and SoCs • Altera Documentation and Resources Center This document states that there are 3 operational modes for tensor mode: 1. Tensor float point mode 2. Tensor fixed point mode 3. Tensor accumulation mode Does the FPGA AI Suite utilize any of these? I also noticed the module uses a FSM and controller.gdb server problem when debugging
Hello, I'm running Quartus12.0sp2 on a windows 11 computer and I want to use the nios 2 eclipse tools to build, run and debug. Building and running works, but I encounter a problem with debugging via usb blaster. I get the error message 'Error starting gdbserver - see console for details'. If I start nios2-gdb-server.exe manually, I get the error message that two .dll files are missing: 'jtag_client.dll' and 'cygwin1.dll'. Both are present in some subfolders of c:/altera/12.0sp2. This behaviour does not change when I start eclipse or gdbserver from the NiosII command shell. Funnily, there is also a file 'nios2-gdb-server-fs2.exe' in the installation path, which seems to run. I tried tricking, by renaming this file into 'nios2-gdb-server.exe'. If I do so, the error message disappears, but the debugging process stops when trying to download the .elf file, at the step 'Launching: Stop processor if running'. I found an old discussion about a similar problem in the forum: Win7-Problem with NIOS-II debugger, can't start gdbserver | Altera Community - 224719 but there's also no clear solution for me. Has anyone else encountered a similar problem? Or can anyone explain what's the difference between 'nios2-gdb-server.exe' and 'nios2-gdb-server-fs2.exe'? Or does know where I have to change a Path such that gdb-server can find the .dll files? I'm quite lost and would appreciate any help. Thanks, Timo
How to create a Packaged Subsystem in TCL
I am hoping to create a script which will automatically package the IP I am working on as a packaged subsystem. So far, I have automated the creation of an IP directory which describes a new component using a _hw.tcl file and the various source files. I believe the next step is to take this component, instantiate it in a Platform Designer system, and create a Packaged Subsystem using it. I am also hoping that I can parameterise and hide/modify ports of the packaged subsystem, like I can with the _hw.tcl component description. I am encountering a problem; I am running the following command: qsys-script --script=create_packaged_subsystem.tcl --new-quartus-project=my_project_name However, the script fails for the following reason: Error: invalid command name "set_package_property" Here is the script itself (more or less a copy-and-paste from the GUI): package require -exact qsys 26.1 set_package_property NAME "packagename" set_package_property DISPLAY_NAME "PackageName" set_package_property VERSION "1.0" set_package_property GROUP "GroupName" set_package_property DESCRIPTION "A descripton." set_package_property ELABORATION_CALLBACK elaboration_callback set_package_property EXTRACTION_CALLBACK extraction_callback add_fileset synth_fileset QUARTUS_SYNTH fileset_callback "Quartus Synthesis Fileset" add_fileset sim_verilog_fileset SIM_VERILOG fileset_callback "Simulation Verilog Fileset" proc elaboration_callback {} { enable_all_instances } proc extraction_callback {} { extract_modules } proc fileset_callback { output_name } { generate_all_instances } Any help would be hugely appreciated, on this issue and on my general workflow. Also if it is possible to encrypt packaged subsystems or components using Quartus I'd be keen to know. Thanks!
DisplayPort Sink (Quartus 18.1) – horizontal pixel offset.
We are experiencing an issue with the DisplayPort Sink IP core (Quartus Prime 18.1), where the captured video stream becomes horizontally shifted after some runtime. The system works correctly after reset, but after a variable period (typically several minutes), the image suddenly shifts horizontally by a constant number of pixels (hundreds of pixels). The image remains stable but shifted. After longer time (tens of minutes), the image may spontaneously recover, and the cycle repeats. This behavior only appears when the input signal is routed through a DisplayPort optical extender (G&D). Without the extender, the system operates correctly and indefinitely stable. This system design is constrained to Quartus 18.1 (cannot migrate easily) - We are primarily looking for a workaround or confirmation of known limitation - Not asking for redesign or migration unless necessary
TSE -> SGDMA -> SOC(through f2sdram)
Hi, I'm trying to transfer an old design with multiple TSEs / SGMDAs and a NIOS to a newer Agilex 5. We are also evaluating the use of the SOC instead of the NIOS in the design. I've made a minimized platform design for it but it fails during synthesis with the notorious error for the f2sdram bus: There is both a 'memory -> streaming' and 'streaming -> memory' sgdma in the design present, so both read and write port on the axi bus should be present. If I connect the SGDMA's to the fpga2hps bus the same error is generated. Are there settings in the SGDMAs that needs to be set to a certain value so that the correct read/write avalon MM/AXI interface is generated?
Is there any way to script the creation of a signal tap instance?
I have been trying to see if it is possible to create a signal tap instance using a scripted approach. For example, create an instance, add some signals from the design using wildcards, setup triggers etc. But I can't seem to find an API for this - does it exist? I have seen that there are scripting APIs for interacting to an existing running signal tap instance, but that isn't what I'm looking for. I could script the creation of a "signal tap logic analyser" IP instance and then instantiate that in HDL code in my design. However that seems quite heavy - adding it do different parts of the design becomes cumbersome and I don't want to keep them in my codebase. The use case is I want to have a collection of debugging nodes that I can conditionally insert and quickly change the configuration of, without cluttering my main RTL. Thanks!LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello, I have a simple design for Agilex 5, using NIOS V/g and EMIF IP with LPDDR4 memory. I have the NIOS V instruction and data manager ports connected to the EMIF IP. Design compiles Ok. But when I create a BSP, in the linker section, there is not a memory device for the LPDDR4. In this thread, a similar problem seems to be mentioned - issue-with-bsp-creation-for-nios-vm-using-lpddr4-on-agilex-5-quartus-24-1--24-3 Does it mean that Address Span Extender IP must be used in order to have the LPDDR4 show in the linker script section, as an available memory device?
