Unique ID registers in Cyclone V
Hello everyone, I need to uniquely identify individual devices at runtime from the HPS (ARM Cortex-A9) side. Does the HPS side of the Cyclone V SoC have any built-in unique ID registers, such as: - A hardware serial number - A unique device ID - OTP (One-Time Programmable) fuses with unique identifiers - Any factory-programmed identification values What I've Tried: I've reviewed the Cyclone V documentation but haven't found clear information about unique ID registers accessible from the HPS side (unlike some other ARM SoCs that have dedicated UID registers). However I have seen Unique ID present in the FPGA side (https://www.intel.com/content/www/us/en/docs/programmable/683336/20-3/cores-user-guide.html), but this is not useful for my use case. Any guidance, documentation references, or code examples would be greatly appreciated! Thanks in advance!
Looking for guidance on CXL IP access (university research, Agilex 7 I-series)
Our lab is currently conducting research on CXL-based systems, and we would like to use Altera’s CXL IP in our work. We already have an Agilex 7 I-series Development Kit, and we intend to integrate the CXL IP for non-commercial, academic research purposes only. However, when we contacted distributors such as Mouser and Digi-Key, we were informed that CXL IP is not available for sale in Korea now. Could you please let us know: 1. Whether CXL IP is available under a university license or academic program, 2. What the procedure is for a university in Korea to obtain or purchase the CXL IP (including any required forms, NDAs, or eligibility criteria), If there is a specific sales representative or regional contact we should speak with, we would appreciate it if you could connect us or share their contact information. Thank you very much for your time and support. I look forward to your guidance.
How to reduce ROM/RAM requirements for a NIOSV Compact CPU Platform?
Hello ALTERA NIOSV Experts, I am trying to create a system in Quartus Platform Designer which has the following components: A 1G Tri mode ethernet IP (with 32 bit AVALON-ST TX/RX interfaces using minimum sized FIFOs) A RS 232 UART with no FIFO A couple of small FIFOs using AVALON-ST interfaces for data in and out of Platform via Conduits A NIOSV Compact CPU A JTAG UART ROM for NIOSV RAM for NIOSV My questions are about how to reduce the ROM (for the NIOSV compacts program) and RAM to the minimum amount. I am trying to shoehorn this all into a MAX10 FPGA ( Altera Max 10 part number 10M08SAU169I7G). When i build the BSP for this platform, with a "Hello World" program, it seems to need around 128 Bytes of ROM and several KBytes of RAM. Why is the program so large ? I expect it has to do with the BSP adding in drivers for all the Platform IP and it is getting bloated. What tactics are available for me to use in the Ashling RISC FREE IDE which i am using to create my BSP and/or Platform Designer to reduce the program size ? The FPGA i am trying to use only has around 48 K Bytes of RAM available in total ...so maybe this is not possible and i need a bigger FPGA of course ! Thanks for your help, Dr BarryCreated Free NIOSV IP evaluation license but did not get any license file by email?
Hi ALTERA NIOSV experts, I have created licenses (the free evaluation type) through the Intel Altera Licensing portal for NIOSV-c, NIOSV-g, and NIOSV-m IP types. I get 3 messages saying a license has been created and i can see all the correct fields are filled in on the license form each time. It then says you will get a license by email. But after 2 hours i still have not received anything from Intel-Altera. Is there a problem with this licensing platform ?Is there a time delay between creating a license and actually getting it by email ? Usually this occurs very quickly, but not in this case ! Any suggestions or help much appreciated ! Thanks, Barry
How to use SDRAM IP core on Agilex 3?
I am testing my project on Atum Nios V starter kit from terasic, which bases on Agilex 3 (A3CZ135BB18AE7S) and SDRAM(IS42VM32160G-6BLI). my purpose is, realize a Nios V system with RTOS and use the SDRAM as the program ram of the RTOS. My question: Agilex 3 is supported only by the higher version such as quartus pro 25.3, and the SDRAM ip is supported by previous old version quartus. do you have any solution that i can reuse the avalon interface SDRAM IP core on Agilex 3? thanks.Creating a design with a 1G Ethernet IP for Synthesis
Hello QUARTUS IP experts, I need to build a project which has a Triple Speed Ethernet IP in using QUARTUS Standard edition and Platform Designer. I can create an example design and i have been able to simulate that in QUESTA. But what is the best method to create a design which has the correct AVALON MM and AVALON ST modules connected up for the Control, Status, MDIO, and TX and RX paths ? Is there an ALTERA Github somewhere which already has this kind of test design built ? I am using a MAX10 FPGA and System Verilog. My aim is to be able to synthesise and implement this test design so that i can see the LUT and memory utilizations a couple of different configuration, using the 1G speed. Thanks for your help, Barry
Clock Domains and Clock Domain Crossing (CDC)
The FPGA design uses two clock domains: 100 MHz and 40 MHz. Clock domain crossing (CDC) between these domains is handled as follows: Data transfer (100 MHz → 40 MHz): A FIFO is used to provide reliable synchronization and maintain data integrity during transfers from the faster to the slower clock domain. Control signals (100 MHz ↔ 40 MHz): Shift-register synchronizers are used to safely transfer control signals in both directions between the two domains. The CDC implementation follows the recommendations outlined in the Altera Clock Domain Crossing tutorial. The main question concerns how timing constraints are applied: 1-Do the set_max_skew and set_data_delay constraints have any impact after defining the following asynchronous clock-group constraint? set_clock_groups -asynchronous -group {clkA} -group {clkB} 2-Additionally, how should the multiplier values (e.g., 0.8 or 0.9) used in set_max_skew and set_data_delay be determined or selected? Thanks.USB blaster not detected in Quartus 24.1
Hi, Recently updated from windows 10 to windows 11. Previously was using Quartus 19.1 and after upgrade USB blaster driver got corrupted. Below are the steps I did to debug the issue: Update driver via enforce driver disable in windows. Load usb blaster driver of quartus 24.1 Uninstall quartus 19.1 and USB blaster drivers. Installed Quartus 24.1 and USB blaster driver that came with it. Even after step 3, same issue. How can I solve it? Even though Quartus 24.1 USB blaster is supported in windows 11. Device Manager Error reporting when USB blaster is connected. Signal Tap doesn't recognize any hardware connected.
