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miscellaneous-mice's avatar
miscellaneous-mice
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1 month ago
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Unique ID registers in Cyclone V

Hello everyone,

I need to uniquely identify individual devices at runtime from the HPS (ARM Cortex-A9) side.

Does the HPS side of the Cyclone V SoC have any built-in unique ID registers, such as:
- A hardware serial number
- A unique device ID 
- OTP (One-Time Programmable) fuses with unique identifiers
- Any factory-programmed identification values

What I've Tried:
I've reviewed the Cyclone V documentation but haven't found clear information about unique ID registers accessible from the HPS side (unlike some other ARM SoCs that have dedicated UID registers).

However I have seen Unique ID present in the FPGA side (https://www.intel.com/content/www/us/en/docs/programmable/683336/20-3/cores-user-guide.html), but this is not useful for my use case.

Any guidance, documentation references, or code examples would be greatly appreciated!

Thanks in advance!

Arm Processor
general
Hps Arch
  • JitLoonL_Altera's avatar
    JitLoonL_Altera
    1 month ago

    Hi, 


    A number of identification mechanisms exist on Cyclone V devices, but none of them function as a dedicated, per-device hardware serial number on the HPS side in the same way some other SoCs provide. What is available depends on which part of the chip you are accessing.

    JTAG IDCODE

    Cyclone V devices include a 32-bit IEEE 1149.1 IDCODE, and the documentation lists the values for each family member. This code identifies the device type, variant, and revision, which can be useful for checking what device is present in a chain. However, the IDCODE follows a fixed format (version + part number + manufacturer), so it does not differentiate one physical device from another of the same model.

    System Manager registers

    The HPS System Manager exposes some identification fields such as silicon revision, but the available fields generally describe the device class rather than provide a unique per-unit identifier. The fields tend to be constant across all devices of the same family/stepping.

    FPGA-side Unique ID

    There is also a Unique Chip ID feature available in the FPGA fabric through specific Intel IP. This can be used to retrieve a value that is tied to the FPGA die. If HPS access is required, it can be bridged into the HPS through lightweight AXI/Avalon interfaces. Whether this meets the use-case depends on the system architecture.

    Board-level alternatives

    Some systems instead rely on identifiers stored outside the SoC—for example:

    eMMC CID registers

    QSPI/NAND flash locations provisioned during manufacturing

    External EEPROM with a programmed serial number

    These methods provide stable per-unit identification when a silicon-level ID is not exposed.

3 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Hi,

    as you already stated, various ARM 9 implementations have vendor specific unique ID features. Cyclone V HPS documentation doesn't mention such a feature. As you can access unique ID IP in FPGA fabric with a bit of platform designer programming, I don't expect a second access path through HPS register.

    I guess your use case wants to avoid loading a FPGA configuration before accessing unique ID? You may also check if the flash memory of your design provides an unique ID.

  • JitLoonL_Altera's avatar
    JitLoonL_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    1 month ago

    Hi, 


    A number of identification mechanisms exist on Cyclone V devices, but none of them function as a dedicated, per-device hardware serial number on the HPS side in the same way some other SoCs provide. What is available depends on which part of the chip you are accessing.

    JTAG IDCODE

    Cyclone V devices include a 32-bit IEEE 1149.1 IDCODE, and the documentation lists the values for each family member. This code identifies the device type, variant, and revision, which can be useful for checking what device is present in a chain. However, the IDCODE follows a fixed format (version + part number + manufacturer), so it does not differentiate one physical device from another of the same model.

    System Manager registers

    The HPS System Manager exposes some identification fields such as silicon revision, but the available fields generally describe the device class rather than provide a unique per-unit identifier. The fields tend to be constant across all devices of the same family/stepping.

    FPGA-side Unique ID

    There is also a Unique Chip ID feature available in the FPGA fabric through specific Intel IP. This can be used to retrieve a value that is tied to the FPGA die. If HPS access is required, it can be bridged into the HPS through lightweight AXI/Avalon interfaces. Whether this meets the use-case depends on the system architecture.

    Board-level alternatives

    Some systems instead rely on identifiers stored outside the SoC—for example:

    eMMC CID registers

    QSPI/NAND flash locations provisioned during manufacturing

    External EEPROM with a programmed serial number

    These methods provide stable per-unit identification when a silicon-level ID is not exposed.

  • miscellaneous-mice's avatar
    miscellaneous-mice
    Icon for New Contributor rankNew Contributor
    1 month ago

    Thanks for the response. Yes, my use case avoids loading the FPGA ID, because I need to retrieve the FPGA ID before the uboot loads the FPGA image from flash into SRAM.