Forum Discussion
New ContributorWhy does the system report an error when generating rbf from sof files and fsbl files?
Error message:
Error: Internal Error: Sub-system: BITASM, File: /quartus/pgm/bitasm/bitasm_common_code.cpp, Line: 518 HPS data start address(-1950584) is not 16 aligned
Device and tool information：
- The device used is Stratix 10 1SX110HN2F43I2VG, without using the Stratix 10 SoC Development Kit；
- Quartus Prime Pro25.1.1
- U-boot source code：u-boot-socfpga-socfpga_v2025.04
- ATF source code：arm-trusted-firmware-socfpga_v2.13.0
Operation steps：
- Simplified the Platform Designer section of the Stratix 10 GHRD project；
- 【Device and Pin Options】->【Configuration】Set the HPS/FPGA configuration order to be HPS First；
- The Quartus full compilation generates the sof file in the "output_files" directory；
- Compile the ATF source code, and obtain the bl31.bin file in the path of ./build/stratix10/release；
- Copy the bl31.bin file to the root directory of u-boot, compile the u-boot source code, and obtain the u-boot-spl file in the ./spl/ directory；
- Convert u-boot-spl to u-boot-spl.hex and copy it to the output_files directory；
Open the Programming File Generator tool and configure the Output Files：
- Configure Input Files, add sof and HEX files：
9. Configuration Device：
10. Generate error：
20 Replies
EstebanVV_AlteraOccasional Contributor
Just realized you are converting the u-boot-spl file as well, please try using u-boot-spl-dtb.hex, as suggested in the command
gritok，the 7th and 9th steps in the "Operation Steps" remain unchanged. For the 8th step, replace the HPS File with u-boot-spl-dtb.hex.
The generation process was successful. What's the reason for this? It's truly astonishing. It seems that there is no information suggesting that u-boot-spl-dtb.hex is required.
- EstebanVV_Altera
Yes, my guess is that your conversion as you said in "6. Convert u-boot-spl to u-boot-spl.hex and copy it to the output_files directory" is not aligned, hence the error.
Now, the current information and the recommended flow is the one described in the links I shared with you https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#build-core-rbf and https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/fabric-config/ug-linux-fabric-config-s10sx-soc/#build-example
Anyways, I have raised a issue internally so this is better handled by Quartus Programmer instead of a crash.
~E.V.
- EstebanVV_Altera
Looking into this...
- EstebanVV_Altera
While I'm investigating if this is a bug in Quartus. Could you try using:
>> quartus_pfg -c <NAME>.sof <NAME>.jic -o device=<DEVICE_NAME> -o flash_loader=<LOADER_NAME> -o hps_path=u-boot-spl-dtb.hex -o mode=ASX4 -o hps=1
Please double ceck your procedures are inline with
https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#build-core-rbf and https://altera-fpga.github.io/rel-25.3/embedded-designs/stratix-10/sx/soc/fabric-config/ug-linux-fabric-config-s10sx-soc/#build-example
~E.V.
- grit
Thank you for your reply.
I noticed that the "Build Hardware Design" section in the link would generate two sof files, namely *.sof and *_hps_debug.sof. However, on my end, I don't have the *_hps_debug.sof file.
Could it be that there is something wrong with my project settings?
Here, I can only attempt to convert the file to the jic format using the only_HPS_Baseline.sof file.
The result reported an error. The .sof file is missing the HPS bootloader information.
- EstebanVV_Altera
Hi!
This is failing because you are missing " -o hps_path=u-boot-spl-dtb.hex"
~E.V.
