hps debug

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Cyclone V HPS FPGA2SDRAM Clock Queries
Dear Intel and all, Having some very puzzling behavior on HPS SDRAM and FPGA fabric bridge. If a fast clock i.e. 148MHz is running on 128bit AXI3 aka f2h_sdram0 mostly read action. And another AXI3 is using the remain 128bit bus with 144MHz aka f2h_sdram1 mostly on write. As such the system will stuck on distro aka Linux. With all these background could engineer or internal stuffs help. What is the restriction or constraints to use these bus under safe and stable speed? Forgot to provide stable situation: If the write dominated bus is reduced to 100MHz then the system is stable and no stall is found. So this makes a very strong feeling that the write cache is having issue? maybe CMA insufficient? Brian
BrianSune_Froum
7 hours ago Place SoC System
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Sending serial commands on DB9 Arria 10 SoC FPGA
I am attempting to send serial based commands using the RS-232 protocol on the DB9 connector on the Arria 10 but do not know which device to use within my C program. I've opened "/dev/tty0" and can send appropriate commands "AT+CGMM\r" but these commands are sent out the J10 UART1 (HPS) on the board and not the DB9. I'm unable to read "/dev/ttyS1" within my c program. I've tried various other devices without luck. I've also set status to "okay" on serial0@ffc02000. In file: ./arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts and rebuild the dtb and placed on SD card. I've looked in Non-8250 serial port support in .config but haven't modified the kernel. Previously, I did enable the FTDI in the kernel for another device and got that working correctly. Any suggestions will be greatly appreciated. Thank you. stty -F /dev/ttyS1 stty: /dev/ttyS1: Input/output error
sfillingim
17 days ago Place SoC System
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Agilex 5 EMAC GMII loopthrough: signals are not toggling in Fabric
I am trying to route GMII signals through the Agilex5 HPS to the Fabric. In the .dts I am using, I have the following settings for the two EMACs: &gmac0 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; // must be added, and if no PHY, then add fixed link //phy-handle = <&emac0_phy0>; max-frame-size = <9000>; fixed-link { speed = <1000>; full-duplex; }; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; emac0_phy0: ethernet-phy@0 { reg = <0>; }; }; }; &gmac1 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; //phy-handle = <&emac1_phy0>; max-frame-size = <9000>; fixed-link { speed = <1000>; full-duplex; }; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; emac1_phy0: ethernet-phy@0 { reg = <0>; }; }; }; In the RTL I am connecting the two EMACs as followed: logic user_clk_pll_125, user_clk_pll_25, user_clk_pll_2_5; // 1G / 100M / 10M (* noprune *) logic [7:0] tx_dummy_counter; (* noprune *) logic emac0_mac_tx_clk_o_wire, emac0_mac_tx_clk_i_wire, emac0_mac_rx_clk_wire, emac0_mac_rst_tx_n_wire, emac0_mac_rst_rx_n_wire; (* noprune *) logic emac0_mac_txen_wire, emac0_mac_txer_wire, emac0_mac_rxdv_wire, emac0_mac_rxer_wire, emac0_mac_col_wire, emac0_mac_crs_wire; (* noprune *) logic [7:0] emac0_mac_rxd_wire; (* noprune *) logic [2:0] emac0_mac_speed_wire; (* noprune *) logic [7:0] emac0_mac_txd_o_wire; (* noprune *) logic [7:0] rx_dummy_counter; (* noprune *) logic emac1_mac_tx_clk_o_wire, emac1_mac_tx_clk_i_wire, emac1_mac_rx_clk_wire, emac1_mac_rst_tx_n_wire, emac1_mac_rst_rx_n_wire; (* noprune *) logic emac1_mac_txen_wire, emac1_mac_txer_wire, emac1_mac_rxdv_wire, emac1_mac_rxer_wire, emac1_mac_col_wire, emac1_mac_crs_wire; (* noprune *) logic [7:0] emac1_mac_rxd_wire; (* noprune *) logic [2:0] emac1_mac_speed_wire; (* noprune *) logic [7:0] emac1_mac_txd_o_wire; assign emac0_mac_rx_clk_wire = emac1_mac_tx_clk_o_wire; // 1G assign emac1_mac_rxdv_wire = emac0_mac_txen_wire; assign emac1_mac_rxer_wire = emac0_mac_txer_wire; assign emac1_mac_rxd_wire = emac0_mac_txd_o_wire; assign emac1_mac_col_wire = 1'b0; assign emac1_mac_crs_wire = 1'b0; assign emac0_mac_rx_clk_wire = emac0_mac_tx_clk_o_wire; // 1G assign emac0_mac_rxdv_wire = emac1_mac_txen_wire; assign emac0_mac_rxer_wire = emac1_mac_txer_wire; assign emac0_mac_rxd_wire = emac1_mac_txd_o_wire; assign emac0_mac_col_wire = 1'b0; assign emac0_mac_crs_wire = 1'b0; The GMII signals are exported from the Agilex HPS as followed: When the system boots, the following can be seen is dmesg: [ 1.443647] socfpga-dwmac 10810000.ethernet: Adding to iommu group 0 [ 1.450679] socfpga-dwmac 10810000.ethernet: IRQ eth_wake_irq not found [ 1.457291] socfpga-dwmac 10810000.ethernet: IRQ eth_lpi not found [ 1.463542] socfpga-dwmac 10810000.ethernet: RX VLAN HW Stripping [ 1.469741] socfpga-dwmac 10810000.ethernet: SMTG Hub Cross Timestamp supported [ 1.477398] socfpga-dwmac 10810000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.484534] socfpga-dwmac 10810000.ethernet: XGMAC2 [ 1.489489] socfpga-dwmac 10810000.ethernet: DMA HW capability register supported [ 1.496943] socfpga-dwmac 10810000.ethernet: RX Checksum Offload Engine supported [ 1.504396] socfpga-dwmac 10810000.ethernet: COE Type 1 [ 1.509603] socfpga-dwmac 10810000.ethernet: TX Checksum insertion supported [ 1.516623] socfpga-dwmac 10810000.ethernet: TSO supported [ 1.522089] socfpga-dwmac 10810000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.530076] socfpga-dwmac 10810000.ethernet: device MAC address 42:ca:f5:1e:55:80 [ 1.537533] socfpga-dwmac 10810000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.544737] socfpga-dwmac 10810000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.551847] socfpga-dwmac 10810000.ethernet: TSO feature enabled [ 1.557831] socfpga-dwmac 10810000.ethernet: SPH feature enabled [ 1.563815] socfpga-dwmac 10810000.ethernet: TX COE limited to 2 tx queues [ 1.570665] socfpga-dwmac 10810000.ethernet: Using 40/40 bits DMA host/device width [ 1.581335] socfpga-dwmac 10820000.ethernet: Adding to iommu group 1 [ 1.588338] socfpga-dwmac 10820000.ethernet: IRQ eth_wake_irq not found [ 1.594945] socfpga-dwmac 10820000.ethernet: IRQ eth_lpi not found [ 1.601179] socfpga-dwmac 10820000.ethernet: RX VLAN HW Stripping [ 1.607380] socfpga-dwmac 10820000.ethernet: SMTG Hub Cross Timestamp supported [ 1.614905] socfpga-dwmac 10820000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.622027] socfpga-dwmac 10820000.ethernet: XGMAC2 [ 1.626982] socfpga-dwmac 10820000.ethernet: DMA HW capability register supported [ 1.634436] socfpga-dwmac 10820000.ethernet: RX Checksum Offload Engine supported [ 1.641890] socfpga-dwmac 10820000.ethernet: COE Type 1 [ 1.647097] socfpga-dwmac 10820000.ethernet: TX Checksum insertion supported [ 1.654117] socfpga-dwmac 10820000.ethernet: TSO supported [ 1.659583] socfpga-dwmac 10820000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.667568] socfpga-dwmac 10820000.ethernet: device MAC address 3e:47:0a:4f:7b:96 [ 1.675024] socfpga-dwmac 10820000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.682221] socfpga-dwmac 10820000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.689330] socfpga-dwmac 10820000.ethernet: TSO feature enabled [ 1.695314] socfpga-dwmac 10820000.ethernet: SPH feature enabled [ 1.701298] socfpga-dwmac 10820000.ethernet: TX COE limited to 2 tx queues [ 1.708147] socfpga-dwmac 10820000.ethernet: Using 40/40 bits DMA host/device width [ 1.718293] socfpga-dwmac 10830000.ethernet: Adding to iommu group 2 [ 1.725245] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found [ 1.731850] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found [ 1.738075] socfpga-dwmac 10830000.ethernet: RX VLAN HW Stripping [ 1.744242] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported [ 1.751730] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.758854] socfpga-dwmac 10830000.ethernet: XGMAC2 [ 1.763807] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported [ 1.771261] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported [ 1.778712] socfpga-dwmac 10830000.ethernet: COE Type 1 [ 1.783917] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported [ 1.790936] socfpga-dwmac 10830000.ethernet: TSO supported [ 1.796400] socfpga-dwmac 10830000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.804372] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.811565] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.818673] socfpga-dwmac 10830000.ethernet: TSO feature enabled [ 1.824656] socfpga-dwmac 10830000.ethernet: SPH feature enabled [ 1.830639] socfpga-dwmac 10830000.ethernet: TX COE limited to 2 tx queues [ 1.837487] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width ... [ 11.730428] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 11.747001] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 11.770275] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 11.778338] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 11.782322] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 11.787412] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 11.790998] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 11.796018] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 11.813781] fpga_manager fpga0: Stratix10 SOC FPGA Manager registered [ 11.913063] socfpga-dwmac 10830000.ethernet eth2: PHY [stmmac-2:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL) [ 11.913393] socfpga-dwmac 10830000.ethernet eth2: No Safety Features support found [ 11.913478] socfpga-dwmac 10830000.ethernet eth2: IEEE 1588-2008 Advanced Timestamp supported [ 12.001908] socfpga-dwmac 10830000.ethernet eth2: registered PTP clock [ 12.007839] socfpga-dwmac 10830000.ethernet eth2: FPE workqueue start [ 12.007940] socfpga-dwmac 10830000.ethernet eth2: configuring for phy/rgmii-id link mode [ 12.155854] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 12.159161] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 12.180998] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 12.191086] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 12.199787] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 12.208205] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 12.218464] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 12.229854] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 12.247722] socfpga-dwmac 10820000.ethernet eth1: No Safety Features support found [ 12.247967] socfpga-dwmac 10820000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported [ 12.331440] socfpga-dwmac 10820000.ethernet eth1: registered PTP clock [ 12.332900] socfpga-dwmac 10820000.ethernet eth1: FPE workqueue start [ 12.332987] socfpga-dwmac 10820000.ethernet eth1: configuring for fixed/gmii link mode [ 12.343803] socfpga-dwmac 10820000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off [ 12.344209] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready [ 12.449807] of-fpga-region soc:base_fpga_region: FPGA Region probed [ 12.469882] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 12.479649] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 12.482568] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 12.490255] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 12.493314] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 12.501735] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 12.514200] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 12.536765] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 12.582718] socfpga-dwmac 10810000.ethernet eth0: No Safety Features support found [ 12.583005] socfpga-dwmac 10810000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported [ 12.591157] socfpga-dwmac 10810000.ethernet eth0: registered PTP clock [ 12.601012] socfpga-dwmac 10810000.ethernet eth0: FPE workqueue start [ 12.601201] socfpga-dwmac 10810000.ethernet eth0: configuring for fixed/gmii link mode [ 12.611650] socfpga-dwmac 10810000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off [ 12.615095] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready ... (this log was from testing 100M, but the same occurs for 1G) In signal tap, no wires are toggled (even though it seems the output clocks are fine) Please help!
K606
25 days ago Place SoC System
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Stratix 10 GSRD Development Issues
Currently working with the GSRD Users Guide from the Rocketboards archives (https://altera-fpga.github.io/rel-24.3/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#partial-reconfiguration_1). Have been attempting to try and better understand the Partial Reconfiguration portion of the design and have made some attempts at trying to modify the design and rebuild from there. I've walked through the process fully to get the initial build fully developed and working. I then attempted to edit the top level of the design by disconnecting the user LEDs from the Qsys Top and hard coding their values. I went through the entire process again and replaced the ghrd_s10_top.sv with the LED changes before running "make all". Going through the entire rebuild process and the Yocto rebuild, I produced a JIC and SDCard Image which i loaded the same way as the working build. But when I attempt the "dtbt" device tree to apply either Persona, the command gets stuck and pushes a "Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: timeout waiting for svc layer buffers". Looking for any assistance on the process of applying changes to the design and rebuilding this PR design. Thanks for any assistance
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RLambdin92
1 month ago Place SoC System
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HPS SDRAM Calibration Failed
To whom it may concern, The HPS of a Cyclone V SoC based board that I designed is failing the booting process. In which the following error message is outputted to the console: U-Boot SPL date and time SDRAM Calibration Failed. ERROR ### Please Reset the board ### I’m trying to determine the cause of the SDRAM calibration failure by enabling calibration reporting as indicated in: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/enabling-the-debug-report-for-arria.html https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/determining-the-failing-calibration.html but I’m only getting the above mentioned message without an indication of the failing SDRAM stage and cause. please advise on how to get the preloader to output debug insights to the console. Please note that the approach described in the link below was used to create the Preloader: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 Also, please advise on the sequence of failure messages that are outputted by the Preloader. Regards,
F_A_A
1 month ago Place SoC System
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Arria 10 SoC FPGA
I have a Arria 10 SoC FPGA. From the board, I am connected to the ethernet port, HPS debug UART, and USB blaster cable. From a PC I am able to communicate to the board across all three interfaces. The HPS sends serial data and I'm able to write basic scripts to modify the LEDs and the LCD along with the push buttons using either the actual memory locations for name based locations under /sys/class/... I have a Furuno GT-100 GPS connected to the HPS-USB port. It uses a USB-C FTDI cable to output serial information. When connected to a linux PC, I'm able to see the serial output just fine setting the device accordingly. But, I am unable to see any serial information on the Arria 10. The arria 10 itself does NOT identify the USB/COM connection when connected as the PC does. This does not allow me to open the device under tty. But, from the dmesg, the kernel does identify the device as a USB 2.0 but doesn't assign any device. I've tried modifying the device tree and added the Furuno to the compatible devices and I've also attempted to access the memory directly using the base address of the USB(s) without any luck. The serial uses the standard baud of 115200 which I also added to the device tree. My overall goal is to read the serial data, parse the coordinates and display to the LCD. The latter of the two I've already done so to speak, but I haven't been able to read the data. My HPS-USB cable is connected to J4 on the board. I've also modified some of the jumpers to see if that was the issue but I don't believe so. The HPS-USB is able to identify a standard flash drive without any problems.
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sfillingim
1 month ago Place SoC System
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Main Features Released in 25.1.1
Main Features Released in 25.1.1: Initial support of the Agilex 3 device. Released GSRD for the Agilex 3 C-Series Development Kit. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/ DDR ECC support in the Agilex 5. Support of production Agilex 7 F-Series Crypto device. GSRD for DK-DEV-AGF0123FA dev kit (using production AGFD023R24C2E1VC ) replaces the DK-DEV-AGF027F1ES dev kit (using engineering sample AGFB027R24C2E2VR2). Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-7/f-series/fpga/gsrd/ug-gsrd-agx7f-fpga/ Support of USB 3.1 in Agilex 5 GSRDs. Support of booting from eMMC in ATF to Linux Direct boot for Agilex 5 device. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-emmc_1 Removed generation of NAND binaries in Agilex 5 GSRD. Will be re-enabled when production devices get released.
RolandoS_Altera
4 months ago Place SoC System
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Baremetal Example SDMMC makefile failed
Hello, CycloneVsoc with BM environment, SOCEDS 20.1 and ARMDS 2021 I downloaded your bare-metal SDMMC sample, but the build failed when using ARMDS make. Here is the error message: make all arm-altera-eabi-gcc -g -O0 -Wall -Werror -std=c99 -mcpu=cortex-a9 -mfloat-abi=softfp -mfpu=neon -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -Dsoc_cv_av -c sdmmc_demo.c -o sdmmc_demo.o process_begin: CreateProcess(NULL, arm-altera-eabi-gcc -g -O0 -Wall -Werror -std=c99 -mcpu=cortex-a9 -mfloat-abi=softfp -mfpu=neon -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -Dsoc_cv_av -c sdmmc_demo.c -o sdmmc_demo.o, ...) failed. make (e=2) Before making I've point the SOCEDS_DEST_ROOT to my SOC path. And I've opened the embedded_command_shell. Thank you Alex
CAlex
5 months ago Place SoC System
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Software Development Tools
What is the difference in software development between ARM-DS for Altera and Ashling RiscFree IDE?
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Njoroge
6 months ago Place SoC System
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Inquiry about Transferring DS-5 Node-Locked License
Hello, I would like to transfer the DS-5 node-locked license from my old laptop to a new one. However, I have lost the account credentials (username and password) from the original purchase. Currently, I can only provide the host IDs and the license.lic file. I would like to inquire if it is possible to transfer the license to the new laptop under these circumstances. If transferring is not possible, could you provide information on the cost of repurchasing the license? Additionally, we are currently using the DS-5 Altera Edition. Thank you. Best regards, Judy
judy_yu
1 year ago Place SoC System
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