Forum Discussion
ContributorCyclone V HPS FPGA2SDRAM Clock Queries
Dear Intel and all,
Having some very puzzling behavior on HPS SDRAM and FPGA fabric bridge.
If a fast clock i.e. 148MHz is running on 128bit AXI3 aka f2h_sdram0 mostly read action.
And another AXI3 is using the remain 128bit bus with 144MHz aka f2h_sdram1 mostly on write.
As such the system will stuck on distro aka Linux.
With all these background could engineer or internal stuffs help.
What is the restriction or constraints to use these bus under safe and stable speed?
Forgot to provide stable situation:
If the write dominated bus is reduced to 100MHz then the system is stable and no stall is found.
So this makes a very strong feeling that the write cache is having issue? maybe CMA insufficient?
Brian
9 Replies
tehjingy_AlteraRegular Contributor
Hi
I am tehjingy_Altera, and I will be helping you with your issue.
Does the Linux distro hang every time the f2sdram_bridge is accessed?
Could you elaborate more on the behavior?
BrianSune_FroumOk, more info for this situation.
KEY 1: If data is kept reading on f2h_sdram0 148M no issue is found.
Once the f2h_sdram1 is enable via some control and start stream at 144M the system stall on distro.
However, the data r/w on bus f2h_sdram0 andf2h_sdram1 are functioning properly.
The only issue is the system aka the CPU is stall and terminal no longer response.
The most interesting thing is that the background FPGA fabric are all functioning like free-run w/o any stall or data stuck.
Well the same design with only slowing down the f2h_sdram1 from 144M to 100M fixed all the issue.
f2h_sdram0 <- mostly read
f2h_sdram1 <- mostly write
So when 144M is used onf2h_sdram1 and once the CPU is stall. All data read / write are still working.
read streams write streams are all functioning via some interface to verify.Brian
- tehjingy_Altera
Hi Brian,
There is no definitive answer for the maximum frequency of the F2SDRAM bridge.
For Cyclone V, F2SDRAM bridge access is managed by the SDRAM subcontroller system, and the operating frequency for the L3 Interconnect, which the F2SDRAM bridge uses has a maximum clock rate of 400 MHz for the -1V speed grade.
https://www.intel.com/content/www/us/en/docs/programmable/683801/current/hps-clock-performance.html
The available throughput is shared among all F2SDRAM bridges instantiated in the system. As more bridges are added, we will need to reduce the input frequency to ensure reliable operation and to stay within the total bandwidth limits.
Please also note that the above calculation is theoretical. In practice, real-world throughput may be lower due to various system factors.
Regards
Jingyang, Teh
