Agilex 5 premium board - es version - boots with gibberish prompts
Hello dear community, I am trying to boot linux on the Altera Agilex 5 premium board - es version with the pre-built binaries. I followed the documentation still getting prompts in gibberish. Following is a detailed description of the procedure I used. My questions: 1. What am I doing wrong? 2. What should be my debugging flow steps? Detailed description of the procedure to demonstrate the issue: --------------------------------------------------------------------- In order to verify the Agilex 5 SoC premium baord is booting correctly, I used the pre-build binaries per the following instructions of this link: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd- agx5e-premium/#configure-serial-console I followed the paragraphs starting with the title " Exercising Prebuilt Binaries" This page instructs the user to download the pre-built binaries from this release: https://releases.rocketboards.org/2025.08/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ I followed the instructions of "Booting from SD card". The workstation is Windows 10 machine and the Terminal application is putty. Eventually, when booting the linux per these instruction, I see the first stage boot loader (u-boot spl) is prompting correct font, however the next booting stages are prompting gibberish. Attached is a screenshot (202604262215screenshot.jpg).55Views1like2CommentsSupport Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap53Views0likes2Commentsrsu_client failing to write to slot
Hello, I am trying to exercise the rsu_client (from Intel's remote system update feature) by erasing a partition on the flash and writing a new file and loading that on the next reboot. This feature works but very very occasionally I encounter an issue where the writing portion fails and the only way that I know to recover from this is to rewrite the flash with the JIC file. I am wondering if someone can advise on how/why this could happen? The feature works robustly most of the time but the said error would require a manual intervention by connecting the JTAG cable. also is it possible to recover from this using the existing rsu_client? I have attached some of the output of the rsu_client for your reference. I do not see any specific message when running `dmesg` on HPS or by inspecting the log in u-boot related to the SPTs/CPBs or QSPI read failure. Note that I do not think this is related to the Flash being worn-out from 1000s of write cycles, the Flash is new and I am seeing this issue on multiple different boards. root@stratix10:~# rsu_client --log VERSION: 0x00000202 STATE: 0x00000000 CURRENT IMAGE: 0x0000000001000000 FAIL IMAGE: 0x0000000000000000 ERROR LOC: 0x00000000 ERROR DETAILS: 0x00000000 RETRY COUNTER: 0x00000000 Operation completed root@stratix10:~# rsu_client --list 0 NAME: P1 OFFSET: 0x0000000001000000 SIZE: 0x01000000 PRIORITY: 1 Operation completed root@stratix10:~# rsu_client --list 1 NAME: P2 OFFSET: 0x0000000002000000 SIZE: 0x01000000 PRIORITY: [disabled] Operation completed root@stratix10:~# rsu_client --list 2 NAME: P3 OFFSET: 0x0000000003000000 SIZE: 0x01000000 PRIORITY: [disabled] Operation completed root@stratix10:~# rsu_client -y DCMF0: OK DCMF1: OK DCMF2: OK DCMF3: OK Operation completed root@stratix10:~# rsu_client -m DCMF0 version = 23.1.0 DCMF1 version = 23.1.0 DCMF2 version = 23.1.0 DCMF3 version = 23.1.0 Operation completed root@stratix10:~# rsu_client --erase 1 Operation completed root@stratix10:~#rsu_client --add application.hps.rpd --slot 1 librsu: priority_add(): Compressing CPB [MED] librsu: erase_dev(): error: Erase length 32768 not erase block aligned [LOW] librsu: writeback_cpb(): error: Unable to ease CPBx [LOW] ERROR: Failed to enable slot Thank you!Solved1.7KViews0likes8CommentsArria 10 SoC – USB devices always enumerating as Full-Speed (Yocto 4.1, dwc2)
Hello, My name is Ángel and I am currently working with an Intel SoC FPGA Arria 10. I am trying to connect an Intel RealSense SR300 camera to my system, but I am experiencing USB speed negotiation issues. Environment: Platform: Intel SoC FPGA Arria 10 OS: Linux (custom image built with Yocto 4.1 Langdale) USB driver: dwc2 librealsense built with -DFORCE_RSUSB_BACKEND=ON When I connect the RealSense SR300 camera, the USB link does not negotiate correctly and the device is always enumerated as Full-Speed (12M) instead of High-Speed or SuperSpeed. At first, I suspected a problem with the USB 3.0 connector of the SR300. However, when I tested with a standard USB 2.0 webcam, I observed exactly the same behavior: the device is still enumerated only as Full-Speed (12M). This suggests the issue is likely related to the USB controller configuration on the Arria 10 rather than the camera itself. System Output lsusb -t: /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=dwc2/1p, 480M |__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=, 12M |__ Port 1: Dev 2, If 1, Class=Audio, Driver=, 12M |__ Port 1: Dev 2, If 2, Class=Audio, Driver=, 12M dmesg: [ 204.765768] usb 1-1: new full-speed USB device number 2 using dwc2 Yocto local.conf: MACHINE = "arria10" DISTRO_FEATURES:append = " systemd vfat" DISTRO_FEATURES:remove = " sysvinit" VIRTUAL-RUNTIME_init_manager = "systemd" IMAGE_INSTALL:append = " kernel-module-uvcvideo" KERNEL_MODULE_AUTOLOAD += "uvcvideo" IMAGE_INSTALL:append = " \ packagegroup-core-boot \ pciutils \ usbutils \ v4l-utils \ i2c-tools \ librealsense2 \ " EXTRA_OECMAKE:append:pn-librealsense2 = " -DFORCE_RSUSB_BACKEND=ON" Any guidance would be greatly appreciated.189Views0likes14CommentsAgilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .48Views0likes0CommentsAgilex5 SD controller in SDR12 mode setup
Hi, According to: https://docs.altera.com/r/docs/814346/25.3.1/hard-processor-system-technical-reference-manual-agilextm-5-socs/clocks?tocId=6fOPkXT1Zba2VR6U1OeQXg It is possible to configure SD controller in SDR12 mode with 25Mhz sdclk for sdcard: The clock to the SD card is the controller clock divided by 2 in these cases, and by 1 in all other cases. I have problem to obtain this setup: In my setup clocks are set as follows: l4_mp_clk = 200MHz (NOC 400Mhz clk /2) softphydiv is 4 so: clk_phy = clk_ctrl = 50Mhz (l4_mp_clk / 4) So controller frequency is 50Mhz. How to configure the SDMMC or COMBOPHY to divide controller clk by 2 for SDR12 mode? I don't see such option in register list: https://www.intel.com/content/www/us/en/content-details/775831/agilex-5-hps-register-map.html and u-boot drivers and devicetreee examples either. https://github.com/altera-fpga/u-boot-socfpga/tree/socfpga_v2025.10 sdhc_cadence, combophy drivers and dts examples in arch/arm/dts How to do this for uboot sd/combophy Cadence driver? With sd-uhs-sdr12 parameter for mmc node I still see 50Mhz on the sd clk pin from HPS to SD card. Marcin Z.129Views0likes4CommentsQuartus Error When No Read Path Exists on F2H Bridge
Hello, I am currently investigating a Quartus compilation error related to the FPGA-to-HPS (F2H) bridge on Agilex 5 devices. [Environment] Device: Agilex 5 Tool: Quartus Prime Pro v25.3 [Issue / Observed Behavior] Connection configuration: mSGDMA (Streaming to MM) -> CCT -> F2H bridge (see attached diagram) HDL generation in Platform Designer completes successfully In the RTL Viewer, the F2H-related logic appears to be instantiated, and the F2SOC_RDATA signal seems to be present in the generated RTL However, during Quartus Prime compilation (Synthesis phase), the following errors occur: [Workarounds / Configuration Changes Tested] To ensure that a Read path toward the F2H bridge exists, we tested the following changes: Connecting the F2H bridge via a JTAG Avalon Master Bridge Changing the mSGDMA DMA mode from "Streaming to MM" to "MM to MM", and connecting mm_read to the CCT Enabling mSGDMA Pre-Fetching Options, and connecting descriptor_read_master / descriptor_write_master to the CCT These changes allow a read-capable master to exist toward the F2H bridge. [Question / Confirmation Point] In a configuration where no read-capable master exists toward the F2H bridge, is it expected (by specification) that Quartus determines the F2H interface as not connected, even if the corresponding signals (e.g. F2SOC_RDATA) appear to exist in the RTL? Even if the design logically requires write-only accesses, is a valid read path master still mandatory for the fpga2hps interface to be considered legally connected? Thank you in advance for any clarification.Solved109Views0likes4CommentsReading S25FL256S OTP region via QSPI Indirect Transfer on Cyclone V HPS — data comes back incorrect
What I'm trying to do I need to read OTP memory region of the S25FL256S flash using command 0x4B. The system normally runs in quad-SPI mode (0xEC, 4-byte address). Since the data I need is more than 8 bytes (STIG limit), I'm trying to use the indirect transfer path. The 0x4B command requires: Single-SPI (1-wire address and data) 3-byte address 1 fixed dummy byte (8 clocks) after address Setup The QSPI controller is initialized at startup using the standard Altera HAL: alt_qspi_init(); // detects flash JEDEC ID, configures timing, sets up qspi_config struct alt_qspi_enable(); // enables controller, sets quad mode (0xEC, 4-byte addr, LC=10b) After this, normal quad-SPI reads via alt_qspi_read() works correctly. What I'm doing Reconfigure controller for 0x4B (OTP Read) ALT_QSPI_DEV_INST_CONFIG_t read_cfg = { .op_code = 0x4B, .inst_type = ALT_QSPI_MODE_SINGLE, .addr_xfer_type = ALT_QSPI_MODE_SINGLE, .data_xfer_type = ALT_QSPI_MODE_SINGLE, .dummy_cycles = 8 }; alt_qspi_device_read_config_set(&read_cfg); ALT_QSPI_DEV_SIZE_CONFIG_t size_cfg = { ... .addr_size = 2, // N+1 encoding → 3 bytes on wire .page_size = 256, ... }; alt_qspi_device_size_config_set(&size_cfg); Disable QUAD on the flash device itself via STIG alt_qspi_read_register(0x35, ®s[1]); // read CR1 alt_qspi_read_register(0x05, ®s[0]); // read SR1 alt_qspi_device_wren(); regs[1] = (regs[1] & 0x3D) | 0x00 | 0x80; // QUAD=0, LC=10b alt_qspi_stig_wr_cmd(0x01, 0, 2, (uint32_t*)regs, timeout); alt_qspi_sr_wait_write(timeout); Execute indirect read // Internally: sets INDRDSTADDR, INDRDCNT, starts transfer, // then CPU drains SRAM FIFO via ALT_QSPIDATA_ADDR alt_qspi_read(dst, src, size); Problem The data returned by the indirect read is incorrect. A STIG-based read of the same region (using the same 0x4B command, 8 bytes at a time) returns the correct data. The indirect read returns wrong/shifted bytes. Hence do I need to configure anything else? Result correct value : 97C5995C5C1E9D5D7A00D4E6BD4ED53E read value : FF97C5995C5C1E9D5D7A00D4E6BD4ED5Solved109Views0likes4CommentsOperating system kernel-level FPGA bridge communication
We are using a custom (Agilex 5) platform and need to access the FPGA bridges from the Linux kernel. We are unable to locate the corresponding device tree nodes or modifications required to access these memory-mapped regions. We're aware of the devmem2 package, but we want to access the FPGA from the kernel side without relying on it. Please guide us on how to configure the device tree and use kernel-level commands or interfaces to access the HPS-to-FPGA and Lightweight HPS-to-FPGA bridges. configuration from Linux. CONFIG_OF_RESOLVE y CONFIG_OF_OVERLAY y CONFIG_OF_CONFIGFS y CONFIG_FPGA_MGR_STRATIX10_SOC y CONFIG_FPGA_BRIDGE y CONFIG_FPGA_REGION y CONFIG_OF_FPGA_REGION y CONFIG_OVERLAY_FS y393Views0likes14CommentsAgilex 5/3 FreeRTOS SDK
Stable Version: v25.4 Quartus Version: 25.3 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4 Release Date: January 16, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS in Agilex 5/3 devices are now available for public. visit the GitHub page for instructions on how to get started. Features and comments Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Feature Agilex3 Agilex5 Supported features Limitations/ Known issues A55 boot Yes Yes Single core boot SMP not supported A76 boot NA Yes Single core boot SMP not supported QSPI boot Yes Yes SD boot Yes Yes eMMC boot Yes Yes NAND boot No No Clk mngr driver Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Write, read and interrupt support Timer driver yes yes User defined and free running modes UART driver yes yes Full duplex Tx and Rx DMA not supported I2C driver Yes Yes Master mode write and read Standard and fast modes DMA not supported I3C driver Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported SPI driver Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes QSPI flash read/write/erase NAND driver No No SDM mailbox driver Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support 100mbps and 1gbps operation USB 2.0 stack NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT yes USB mass storage operation WDT driver Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Error injection and detection Bridge driver NT Yes Enable, Disable Reboot mngr Yes Yes Warm/Cold reboot FPGA manager Yes Yes FPGA configuration Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .297Views1like2Comments