F2SDRAM test inquiries.
Hi Guys, I am testing the F2SDRAM bridge. 32 bit address, 256bits data. Due to recurring missing Verilog file errors for the Qsys adapter IP whenever switching PCs, I removed the adapter earlier and am currently testing by directly exporting f2s from the HPS to the top level. I implemented tester logic on the FPGA side to write and read 256-bit data once per transaction (len=0) for 2048 comparisons, but the B channel signal keeps returning 2'b11 (DECERR). I implemented the tester logic on the FPGA side to perform 2,048 read/write comparison cycles with 256-bit data in single-beat transactions (len=0) using a base address of 0x8000_0000. However, I am at a loss because the B channel signal continuously returns 2'b11 (DECERR). Debugging this solely based on the B channel response is quite challenging. For reference, I am currently running this test on an 013b devkit using the GHRD Linux Reference Design, triggering the start signal via Signal Probe after the kernel has fully booted up Could this be an issue with sideband signals or the kernel driver? Gemini suggests that the bridge might be in reset or it could be due to SMMU. I have already disabled SMMU. As expected, learning and applying new technology is always tough. Thank.
Agilex 5E HPS and Linux
Hi. 1. Is there a simple method to run two Linux systems on HPS, i.e.: Linux 1 - 2xA55 and Linux 2 - 2xA76 with different sets of peripherals? 2. Is it possible to use one Ethernet port by these two Linux systems. 3. Is there a simple method for communication between these two Linux systems?USB Device Issue on Cyclone V / HPS
Hello, Please find below a description of the USB issue we are experiencing with our Cyclone V / HPS board. To test our USB interface, we integrated the TinyUSB library into our existing firmware and enabled FreeRTOS support. Since the Cyclone V is not natively supported, I implemented the missing functions using Altera's hwlib, which we already use in our project (source file attached). The USB is used only in Device mode. I tested the following four configurations: Full-Speed with Slave mode Full-Speed with Simple DMA High-Speed with Slave mode High-Speed with Simple DMA The behavior is identical in all four cases: Connecting our board to a Windows or Linux host is correctly detected. The SETUP transaction is successfully received, and the host receives the device descriptor in response. When the IN transfer complete interrupt is triggered, the USB controller is configured to receive a zero-length packet on OUT0. However, the USB protocol analyzer shows that the device continuously responds with NAK to this packet. The host retries for approximately 5 seconds, but the device keeps responding with NAK. The register values immediately after configuring the reception of the OUT0 packet are: Gotgctl = 0xd00c0 Gintsts = 0x4000020 (PTxFEmp, NPTxFEmp) Gdfifocfg = 0x1f802000 Dctl = 0 Dcfg = 0x8100001 Dsts = 0x18702 Doepctl0 = 0x80008000 Doepint0 = 0 Doeptsiz0 = 0x80000 Grxfsiz = 0x50 After a few milliseconds, I observe that DOEPINT0.NAKINTRPT = 1, which seems to confirm that the device is sending NAKs. However, I do not understand why the OUT packet is not being accepted, since the receive FIFO is not full and both DCTL.GOUTNAKSTS = 0 and DOEPCTL0.NAKSTS = 0.
Agilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .
TSE -> SGDMA -> SOC(through f2sdram)
Hi, I'm trying to transfer an old design with multiple TSEs / SGMDAs and a NIOS to a newer Agilex 5. We are also evaluating the use of the SOC instead of the NIOS in the design. I've made a minimized platform design for it but it fails during synthesis with the notorious error for the f2sdram bus: There is both a 'memory -> streaming' and 'streaming -> memory' sgdma in the design present, so both read and write port on the axi bus should be present. If I connect the SGDMA's to the fpga2hps bus the same error is generated. Are there settings in the SGDMAs that needs to be set to a certain value so that the correct read/write avalon MM/AXI interface is generated?
Altera TOD clock IP with HPS for PTP time sync
We have interfaced the TOD clock IP with Stratix 10 HPS LWH2F bridge with below settings, The LWH2F runs at 100Mhz and the TOD clock is 500Mhz. We need to know, how to load the intial time at startup, how to asjust the time, how to enable the PPS ouput. the PPS ouput is not generated now wven though it is enabel din IP. Complete list of registers with address and function. We are using Quartus Prime Pro 26.1 for development. We plan to use the skyworks accutime software to synchroise the PTP time. The 500Mhz TOD clock is gernated by the si5518 chip.
Unable to receive OUT packet on USB in device mode
Hello, I am trying to use USB on Cyclone V soc with tinyUSB. I am able to receive SETUP transaction and send device descriptor, but then I cannot receive and acknowledge the next OUT transaction. I see that DOEPINT0.nakintrpt goes to 1, confirming that the device responds NAK to the OUT transaction, but I don't understand why. Here are the settings that are relevant to me : GAHBCFG.dmaen = 0 DCTL.sgoutnak = 1 GRXFSIZ.rxfdep = 0x50 DOEPMSK.xfercomplmsk = 1 GINTMSK.rxflvlmsk = 1 Written before waiting for OUT packet: DOEPCTL0.epena = 1 DOEPCTL0.cnak = 1 DOEPTSIZ0.xfersize = 0 DOEPTSIZ0.pktcnt = 1 I am lacking ideas of where to search or what could cause this behaviour. Is there anything to take care ? Best regards, Romain
