Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA

Hi Altera Support Team,

Greetings from Logic Fruit Technologies.

This is Bhanu Pratap and I am working  on the project in which we are using Agilex-7 SOC FPGA.

Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime.

Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. 

Brief Description:

1. We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C).
2. We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version.
3. We are following each step to test GHRD and build generation for the Linux OS.
4. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide.
5. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer.
6. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging.
7. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap.

This looks more like a process gap. We seek your support to fix this issue.

Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap.

Seeking for urgent support.

Thanks

Bhanu Pratap