Agilex5 SD controller in SDR12 mode setup

Hi,

There is no explicit register in the Agilex 5 HPS register map for an additional division by 2 for SDR12. This division is handled internally by the SDMMC controller hardware based on the bus mode.

It seems that the clock division is not occurring, as you are observing 50 MHz on the SD clock pin instead of the expected 25 MHz. This can happen if the U-Boot driver does not properly switch the bus mode to SDR12, or if the driver does not implement the correct configuration sequence for this mode. There is no register to manually divide the clock by 2. The hardware should do this automatically when SDR12 mode is correctly set.

Please confirm in the U-Boot driver logs that the mode is actually set to SDR12 as well as inspect the U-Boot SDMMC driver

https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2025.10/drivers/mmc/sdhci-cadence.c

Reference:

U-Boot socfpga_v2025.10 Source

Agilex 5 HPS Technical Reference Manual: Clocks

Hi Marcin,

The U-Boot MMC subsystem selects the operating mode using a fallback mechanism that tries modes in decreasing order of performance:

1. UHS_SDR104 (208 MHz) - if supported
2. UHS_SDR50 (100 MHz) - if supported
3. SD_HS (50 MHz) - higher priority than SDR12
4. UHS_SDR12 (25 MHz) - lower priority
5. MMC_LEGACY (25 MHz @ 3.3V) - fallback

The driver returns immediately upon finding the first working mode. Therefore, if SD_HS succeeds, SDR12 will never be attempted.

To force the driver to select SDR12 mode, two modifications are needed:

• Device Tree Changes (socfpga_agilex5_socdk-u-boot.dtsi)
  • In the &mmc node, make the following changes:

&mmc {
status = "okay";
no-mmc; disable-wp;
//no-1-8-v; // Remove or keep commented out
//cap-sd-highspeed; // Remove or keep commented out
sd-uhs-sdr12; // Add this property
vmmc-supply = <&sd_emmc_power>;
vqmmc-supply = <&sd_io_1v8_reg>;
max-frequency = <200000000>;
sdhci-caps = <0x00000000 0x0000c800>;
sdhci-caps-mask = <0x00002007 0x0000ff00>;
// ... (rest of PHY timing configuration remains unchanged)
};

Changes explained:

• Remove no-1-8-v: Allows the MMC stack to perform voltage switching to 1.8V, which is required for UHS-I modes
• Remove cap-sd-highspeed: Ensures SDR12 becomes the highest priority mode available
• Add sd-uhs-sdr12: Explicitly declares SDR12 support

• Driver Change (drivers/mmc/sdhci-cadence.c)
  • In the sdhci_cdns_probe() function, add the following quirk:

host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; // Add this line

Changes explained:

This quirk disables SD High Speed mode at the driver level, providing an additional safeguard to ensure SDR12 is selected.

Currently there is no direct method to force the driver to choose SDR12 mode through device tree properties alone. The workaround described above (removing cap-sd-highspeed and adding the quirk) is necessary to achieve SDR12 operation. We will introduce a more straightforward configuration method in a future release to allow direct mode selection without requiring these workarounds.

Please let me know if you need any clarification or have additional questions.

Best regards,
Tze Yee