Agilex5 SD controller in SDR12 mode setup

Hi,

There is no explicit register in the Agilex 5 HPS register map for an additional division by 2 for SDR12. This division is handled internally by the SDMMC controller hardware based on the bus mode.

It seems that the clock division is not occurring, as you are observing 50 MHz on the SD clock pin instead of the expected 25 MHz. This can happen if the U-Boot driver does not properly switch the bus mode to SDR12, or if the driver does not implement the correct configuration sequence for this mode. There is no register to manually divide the clock by 2. The hardware should do this automatically when SDR12 mode is correctly set.

Please confirm in the U-Boot driver logs that the mode is actually set to SDR12 as well as inspect the U-Boot SDMMC driver

https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2025.10/drivers/mmc/sdhci-cadence.c

Reference:

U-Boot socfpga_v2025.10 Source

Agilex 5 HPS Technical Reference Manual: Clocks