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aucamera1's avatar
aucamera1
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2 months ago

HPS f2sdram read/write errors

I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic.

I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus

on the hps_subsys, I exported the f2sdram (AXI4 Subordinate) and connected to my custom logic.

I can perform read and write cycles and everything flows correctly.  I get appropriate response from the f2sdram.

however, on both read and write cycles, the f2sdram responds with the RRESP/BRESP of b11, decode error.

i have tried to read/write to addresses of 0x0000000000, 0x8800000000, and 0xffff000000 and still get the same response error code. 

Anything common that I might have missed in my setup?

20 Replies

  • aucamera1's avatar
    aucamera1
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    2 months ago

    I should also add, that even though the read/write operations otherwise execute successfully, the read back data is random and will change on every read even though its reading the same address.

  • Nirav_Altera's avatar
    Nirav_Altera
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    2 months ago

    Hello aucamera1,

    One clarification: Are you running an FPGA-only design, or is the HPS also being booted (SPL/ATF/U-Boot) before you access F2SDRAM?


      • Yoda_Altera's avatar
        Yoda_Altera
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        2 months ago

        Hello aucamera1,

        I am Jeff, the Agilex 5 HPS / HPS-EMIF expert at Altera.

        1. How much DDR4 do you have attached to the HPS?   8GB?
        2. See the memory map at:  

          https://docs.altera.com/r/docs/814346/25.3.1/hard-processor-system-technical-reference-manual-agilextm-5-socs/total-address-map-graphical

        3. The addresses from the FPGA perspective to SDRAM (F2SDRAM) (blue regions) are: 
          1. 0x00_8000_0000 - 0x01_0000_0000 (first 2 GB of DDR)
          2. 0x08_8000_0000 - 0x10_0000_0000 (next 30 GB of DDR)
          3. 0x88_0000_0000 - 0xFF_FFFF_FFFF (next 480 GB of DDR)
        4. So, please try read/write to somewhere in the range of DDR attached, such as 0x00_8000_0000 (which is really @ 0x0 of the attached DDR) or 0x08_8000_0000 (which is really @ 2GB of the attached DDR).
        5. BUT.... be careful because you could be "modifying" anything that is out in the HPS DDR, such as Linux OS, etc.
        6. Lastly, can you explain what you mean by:
          1. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus

         

        If the above does not work, then we need to focus on making sure the F2SDRAM bridge is properly open and there are no OS blocking issues and/or firewall issues.

        Regards,

        Jeff

    • aucamera1's avatar
      aucamera1
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      1 month ago

      Hi KianHinT_altera​ ,

      no, I haven't had a solution to this problem.  I've gotten a little feed back, but i've also been pulled away from it somewhat.  But overall, I still have this issue.

      • SueC_Altera's avatar
        SueC_Altera
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        1 month ago

        Hi aucamera1,

        Have you been able to try the suggestions from Yoda_Altera below?

        Thanks,

        Sue

  • Yoda_Altera's avatar
    Yoda_Altera
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    1 month ago

    Hi aucamera1,

    1. First, lets make sure you are enabling the bridges properly. 
      1. Are you using the Altera GSRD?
      2. If so,
        1. are booting up to U-Boot and then stopping there to do your reads/writes from your custom logic? 
        2. Or are you booting all the way to Linux to then do your reads/writes from your custom logic?

      3. Please see U-boot commands list at:

        1. https://altera-fpga.github.io/rel-25.3.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-sd-card_1

      4. In the above U-Boot commands list, Here is the boot command that runs bridge enable
        1. CONFIG_BOOTCOMMAND="load mmc 0:1 \${loadaddr} ghrd.core.rbf; fpga load 0 \${loadaddr} \${filesize};bridge enable; mmc rescan; fatload mmc 0:1 82000000 Image;fatload mmc 0:1 86000000 socfpga_agilex5_socdk.dtb;setenv bootargs console=ttyS0,115200 root=\${mmcroot} rw rootwait;booti 0x82000000 - 0x86000000"
      5. Please make sure you run bridge enable command before trying to read/write from your custom logic.

    Regards,

    Yoda (Jeff)

    • aucamera1's avatar
      aucamera1
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      1 month ago
      1. We started with the GSRD, but we've made changes since then.
      2. We're booting all the way into Linux.
      3. The bridge enable command is present in the U-BOOT boot arg configuration. 

       

          We are using HPS-first boot configuration. Is it possible our custom logic is trying to send transactions before the bridge enable has completed its work?

      • Yoda_Altera's avatar
        Yoda_Altera
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        1 month ago

        Ok.  Great.  So, I assume you program the fabric from Linux, right?  If so, then bridge enable will be completed well before the Fabric is programmed (of course).

        Now, you have probably already done this, but just to make sure I am clear, please read/write from your custom logic to address: 

        0x00_8000_0000 (0GB physical DDR)

        0x08_8000_0000 (2GB physical DDR)

        0x09_0000_0000 (4GB physical DDR)

        0x09_8000_0000 (6GB physical DDR)

         

  • KianHinT_altera's avatar
    KianHinT_altera
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    14 days ago

    Hi aucamera1​ ,

    May I know whether your issue has been addressed by Yoda answer? If yes , I will transition this thread to community support for future reference.

    Thanks

    Regards

    Kian